Senior System Level Verification Engineer

Axiado; Hyderabad; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Axiado is seeking a Design Verification Technical Team Lead in Hyderabad to lead chip-level verification for ARM-based System-on-Chip designs, including ROM/FW bring-up and debugging. You will build system-level test environments, develop test plans, and work across teams to root-cause HW issues and validate device drivers and OS boots.

Ideal candidates have 7+ years of DV or validation experience, 5+ years in system-level verification using C, and strong knowledge of SOC architectures and

Qualifications

• 7 years of DV or validation experience.
• 5 years of system level verification experience using C.
• Thorough understanding of CPU and SOC system architecture.
• Proficient in programming and modeling SOC devices (JTAG/UART/SPI/I2C).
• Proficient in test planning and test case development using C.

Responsibilities

• Design verification of ARM-based SoCs and ROM/FW bringup.
• Develop SOC system-level test environments for simulation and emulation.
• Create test plans and tests including error and stress tests.
• Run and debug tests in regressions in simulation and on emulator.
• Collaborate with SW to debug device drivers and OS boots.

Job description

• Full-time

Company Description

Axiado is building the future ofAI powereddigital infrastructure. We are afast-growing,well fundedsilicon, systems, and solutionscompany pioneering a newcategoryofsemiconductor called theTrusted Control/Compute Unit (TCU) that combinesadvanced hardware security,AI drivenresilience and efficiency, andreal-timeplatform management. Our technology protects the world’s most critical infrastructure—from data centers tonext generationcloud and AI platforms—by securing systems at thefoundation levels of hardware, independent of host CPUs and operating systems.

Founded in 2019and now over 150 employeesare strong, Axiado has evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders,validatingboth our technology and our long-term market trajectory.Axiado has also won numerousindustry awards for our ground-breaking products and technological innovations, includingbeing namedone ofFast Company’s 2025 Top 10 Most Innovative Companiesin Security,winning the2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award.

At Axiado, developing breakthrough technology takes more than great engineering—it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world.

Job Description

Design Verification Technical Team Lead position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IOT.

You will be responsible for chip level verification of complex ARM based SOC HW, debugging, and ROM and FW bringup.

Key Responsibilities

Develop SOC system level test environment for simulation and emulation, including log generation, backdoor configuration and device modeling

Develop testplan and tests, including error condition tests and stress tests

Run and debug tests in regressions, both in simulation and on emulator

Work with other teams in root-causing HW issues, and creating system level test cases for them

Validation ROM

Work with SW team in debugging device driver issues, and OS boots

Qualifications

7 years of DV or validation experience, and 5 years of system Level verification experience using C

Has worked through complete project cycle of an SOC ASIC chip

Thorough understanding of CPU and its debug architecture, as well as SOC system architecture

Proficient in programming and modeling typical SOC connected devices, such as JTAG, UART, SPI, I2C.

Proficient in testplanning, test case development using C, and self checking in such tests

Proficient in RTL debugging using waveform viewer

Mastery in C programming, and fluent in scripting languages such as Make, Python, Perl and shell script

Fluent in documentation and issue tracking using Confluence and Jira tools

Preferred experience in

Validation on emulation, FPGA and post-silicon

Complex IP interface validation of USB, Ethernet, PCIE, DDR

Using AI tools in testplanning, generation and debugging

Additional Information

• Experience with SPDM, PLDM, MCTP protocols
• Experience with Caliptra, Crypto/security APIs
• Experience with bootloaders and platform firmware, including initialization, boot flows, reset handling, recovery, and firmware-update mechanisms.
• Understanding of firmware authentication/signature verification, OTP provisioning