SI/PI Packaging Design

HCL Technologies Limited; Bengaluru; On-site; INR 3,500,000 - 6,000,000; Full time

Job summary

HCLTech is seeking an experienced SI/PI Packaging Design Architect with 15+ years of semiconductor packaging expertise. The role focuses on high-speed interface design, package/substrate architectures, EM simulation, and PDN optimization to meet SI/PI/thermal reliability targets.

The incumbent will collaborate with silicon design, package, PCB, RTL/SoC, and manufacturing teams to deliver advanced packaging solutions for HPC, AI accelerators, and network SoCs, while defining guidelines and

Qualifications

• 15+ years experience in semiconductor packaging and SI/PI
• Expertise in high-speed interconnects and PDN analysis
• Proficient in 3D electromagnetic simulation and package extraction
• Experience with FC-BGA, 2.5D/3D IC and HBM integration
• Knowledge of PCIe, DDR, SerDes and Ethernet protocols
• Ability to lead cross-functional teams
• Strong technical communication and mentorship capabilities

Responsibilities

• Lead SI and PI analyses for advanced semiconductor packages and high-speed interconnects.
• Drive package and substrate design optimization for HPC/AI/SoC products.
• Perform pre-layout and post-layout SI/PI analyses including crosstalk and PDN analysis.
• Lead package-to-board co-design activities including bump maps and substrate stack-up.
• Perform EM simulations for high-speed interfaces (PCIe, DDR, HBM, SerDes, Ethernet).
• Optimize PDN, decoupling and impedance profiles.
• Collaborate with package design, RTL/SoC, PCB, thermal and manufacturing teams.
• Define SI/PI design guidelines, simulation methodologies and sign-off criteria.
• Provide technical leadership and root-cause analysis for SI/PI issues.
• Support feasibility studies, technology evaluation and customer reviews.

Skills

SI/PI expertise

Package substrate design

3D EM simulation

EM/PDN sign-off

PCIe

DDR

HBM integration

SerDes

Ethernet

Cadence tools

Ansys HFSS

Ansys SIwave

Clarity 3D Solver

Cross-functional leadership

15+ years experience

Tools

Cadence Sigrity

Cadence Clarity 3D Solver

Ansys HFSS

Ansys SIwave

Job description

Job Description – SI/PI Packaging Design

Company: HCLTech

Experience: 15+ Years

Email: [e-mail]

Domain: Semiconductor Engineering – Signal Integrity, Power Integrity and Advanced Packaging

Job Summary

HCLTech is looking for an experienced SI/PI Packaging Design Architect with 15+ years of experience in signal integrity, power integrity and semiconductor package design. The ideal candidate will have strong expertise in high-speed interface design, package and substrate design, electromagnetic simulation, power delivery network optimization and advanced packaging technologies.

The candidate will work closely with silicon design, package design, PCB, system architecture and manufacturing teams to deliver high-performance semiconductor solutions that meet signal integrity, power integrity, thermal and reliability requirements.

Key Responsibilities

• Lead Signal Integrity (SI) and Power Integrity (PI) analysis for advanced semiconductor packages and high-speed interconnects.
• Drive package and substrate design optimization for high-performance computing, networking, AI/accelerator and SoC products.
• Perform pre-layout and post-layout SI/PI analysis, including crosstalk, insertion loss, return loss, impedance matching and power delivery network (PDN) analysis.
• Lead package-level and package-to-board co-design activities, including bump maps, escape routing, substrate stack-up and interconnect optimization.
• Perform electromagnetic (EM) simulations and analyze high-speed interfaces such as PCIe, DDR, HBM, SerDes, Ethernet and other high-bandwidth interfaces.
• Optimize power distribution networks, decoupling capacitor placement, impedance profiles and simultaneous switching noise.
• Collaborate with package design, RTL/SoC, PCB, thermal, mechanical and manufacturing teams to resolve design challenges.
• Define SI/PI design guidelines, simulation methodologies, sign-off criteria and design review processes.
• Provide technical leadership, mentor engineering teams and drive root-cause analysis for package- and system-level SI/PI issues.
• Support design feasibility studies, technology evaluation, customer reviews and technical proposals.

Required Technical Skills

• 15+ years of experience in semiconductor packaging, signal integrity, power integrity or package/board co-design.
• Strong knowledge of package substrate design, advanced packaging architectures and high-speed interconnect technologies.
• Expertise in SI/PI fundamentals, transmission lines, S-parameters, impedance control, crosstalk, reflections and PDN analysis.
• Hands-on experience with 3D electromagnetic simulation, package extraction and SI/PI sign-off.
• Experience with advanced package technologies such as FC-BGA, 2.5D/3D IC, chiplets and HBM integration.
• Knowledge of high-speed protocols such as PCIe, DDR, HBM, SerDes and Ethernet.
• Proficiency in relevant EDA tools such as Cadence Sigrity, Cadence Clarity 3D Solver, Ansys HFSS, Ansys SIwave or equivalent.
• Understanding of package stack-up, substrate materials, bump/ball assignments, parasitics, thermal constraints and manufacturing considerations.
• Strong problem-solving, technical communication and cross-functional collaboration skills.

Preferred Qualifications

• Experience leading SI/PI architecture, methodology development and technical sign-off for complex semiconductor packages.
• Exposure to advanced packaging for AI, HPC, networking and high-bandwidth memory solutions.
• Experience working with global semiconductor customers and multidisciplinary engineering teams.

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