Senior VLSI Library Characterization Engineer

Sintegra Inc.; Bengaluru; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

Sintegra Inc. in Bengaluru is seeking a Senior VLSI Engineer to characterize standard cell libraries and IPs, and to generate and validate front-end and back-end design kit views.

You will run transistor-level SPICE simulations, analyze timing, power and performance, and perform Monte Carlo analyses. Collaboration with PD, RTL and CAD teams will be essential to resolve kit issues and support tapeouts.

Qualifications

• 6+ years of experience in VLSI / Semiconductor Engineering.
• Hands-on experience in standard cell or IP characterization.
• Strong knowledge of SPICE simulations and CMOS fundamentals.
• Experience with Cadence Virtuoso, HSPICE or Spectre.
• Familiarity with Liberate, PrimeSim, Totem or similar characterization tools.
• Knowledge of PVT analysis, Monte Carlo simulations and Liberty file generation.
• Good scripting skills in Python, TCL, Perl or SKILL.
• Understanding of physical verification, DRC, LVS and design kit development.

Responsibilities

• Characterize standard cell libraries and hard IPs.
• Generate and validate front-end and back-end design kit views.
• Run transistor-level simulations using SPICE, HSPICE or Spectre.
• Work on standard cell timing, power and performance analysis.
• Perform Monte Carlo simulations and high-sigma analysis.
• Collaborate with Physical Design, RTL and CAD teams to resolve design kit issues.
• Support design kit validation, quality checks and test chip tapeouts.
• Work with tools such as Cadence Liberate, PrimeSim DR, HSA and Solido.

Skills

VLSI experience

Characterization (standard cell/IP)

SPICE & CMOS

Cadence tools

Liberate / PrimeSim / Totem

PVT & Monte Carlo

Scripting (Python, TCL, Perl, SKILL)

Physical verification (DRC/LVS)

Tools

Cadence Virtuoso

HSPICE

Spectre

Liberate

PrimeSim

PrimeSim DR

Totem

Solido

Job description

• Perform characterization of standard cell libraries and hard IPs.
• Generate and validate front-end and back-end design kit views.
• Run transistor-level simulations using SPICE, HSPICE or Spectre.
• Work on standard cell timing, power and performance analysis.
• Perform Monte Carlo simulations and high-sigma analysis.
• Work with tools such as Cadence Liberate, PrimeSim DR, HSA and Solido.
• Develop and automate characterization flows using Python, TCL or Perl.
• Collaborate with Physical Design, RTL and CAD teams to resolve design kit issues.
• Support design kit validation, quality checks and test chip tapeouts.

Required Skills:

• 6+ years of experience in VLSI / Semiconductor Engineering.
• Hands-on experience in standard cell or IP characterization.
• Strong knowledge of SPICE simulations and CMOS fundamentals.
• Experience with Cadence Virtuoso, HSPICE or Spectre.
• Familiarity with Liberate, PrimeSim, Totem or similar characterization tools.
• Knowledge of PVT analysis, Monte Carlo simulations and Liberty file generation.
• Good scripting skills in Python, TCL, Perl or SKILL.
• Understanding of physical verification, DRC, LVS and design kit development.

Good to Have:

• Experience with foundry technology and advanced process nodes.
• High-sigma analysis using PrimeSim DR / HSA.
• Experience in test chip design and tapeout.