Power-Domain Verification Lead

Axiado Corp.; Hyderabad; On-site; INR 2,500,000 - 4,500,000; Full time

Job summary

Axiado invites a Verification Lead to drive power-aware simulation and UPF/UVM integration for its cutting-edge Smart Edge SoCs. You will lead RTL/SOC verification efforts, develop constrained-random tests, and ensure robust power domain behavior.

The role requires strong SystemVerilog, UVM expertise, and UPF power-mode modeling, with collaboration across RTL and power architecture teams. Join a fast-growing security/silicon innovator.

Qualifications

• 10+ years in RTL verification with SystemVerilog & UVM.
• Strong UPF/power-intent modeling expertise.
• Experience in power-aware simulation.
• Knowledge of power domains and power states.
• Reset vs power interaction understanding.
• Strong debugging across RTL, UPF, and testbenches.
• Academic credentials: BE/BTech or ME/MTech in EE/EECS/CS.

Responsibilities

• Execute power-aware simulations and debug failures related to power intent.
• Integrate UPF with UVM testbenches and VIPs.
• Expertise in verifying design at RTL (SOC) level and gate-level simulation.
• Create directed and constrained-random tests for low-power scenarios.
• Verify: Isolation, Retention save/restore, Reset behavior across power domains.
• Develop assertions and functional coverage for power states and transitions.
• Support power-aware regression and sign-off.
• Fluency with scripting languages (Make, Perl, Python, Shell).
• Collaborating with RTL, power architects

Skills

SystemVerilog

UVM

Power-aware verification

UPF modeling

Scripting (Python/Perl)

RTL verification

Education

BE/BTech or ME/MTech in EE/EECS/CS

Tools

UPF

Portable Stimulus

Formal verification

RTL/VIP integration

Job description

Axiadois building the future ofAIpowereddigital infrastructure. We are afar stgrowing,wellfundedsilicon, systems, and solutionscompany pioneering a newcategoryofsemiconductor called theTrusted Control/Compute Unit (TCU) that combinesadvanced hardware security,AIdrivenresilience and efficiency, andrealtimeplatform management. Our technology protects the world’s most critical infrastructure—from data centers tonextgenerationcloud and AI platforms—by securing systems at thefoundation levels of hardware, independent of host CPUs and operating systems.

Founded in 2019and now over 150 employeesstrong,Axiadohas evolved into a recognized leader in the convergence of AI, security, and silicon innovation. We partner with and are actively engaged in commercial programs with multiple Tier 1 industry leaders,validatingboth our technology and our long-term market trajectory.Axiadohas also won numerousindustry awards for our ground-breaking products and technological innovations, includingbeing namedone ofFast Company’s 2025 Top 10 Most Innovative Companiesin Security,winning the2025 Global InfoSec Award for Outstanding AI Security Solution, and being named a finalist for the Global Semiconductor Alliance’s 2025 “Start-Up to Watch” award.

AtAxiado, developing breakthrough technology takes more than great engineering—it takes a team of exceptional people who collaborate boldly, challenge assumptions, and take pride in building what comes next. We value curiosity, execution, respect, and a shared desire to make a meaningful impact on the security and reliability of the digital world.

Job Description

Verification Lead Power Aware Simulation position is your opportunity to join one of the industry’s leading companies in Smart Edge SoCs for network/systems control, management security systems, and IIoT.

You should have prior knowledge and experience in power aware simulations with UPF verification and UVM testbench development.

You will be responsible for RTL SoC/Subsystem verification based on ARM CPUs, and work on industry-standard verification methodologies like UVM, Portable Stimulus and Formal verification flows. You will report to the Director of Engineering, Verification.

Key Responsibilities

• Execute power-aware simulationsand debug failures related to power intent
• Integrate UPF with UVM testbenchesand VIPs
• Expertise in verifying design at RTL (SOC) level and gate-level simulation
• Create directed and constrained-random testsfor low-power scenarios
• Verify:
• Isolation
• Retention save/restore
• Reset behavior across power domains
• Develop assertions and functional coveragefor power states and transitions
• Support power-aware regression and sign-off
• Fluency with scripting languages (e.g., Make, Perl, Python, Shell)
• Collaborating with RTL, power architects

Qualifications

• 10+ years of experience with strong hands-on experience with SystemVerilog & UVM
• Solid understanding of UPF / power intent modeling
• Experience with power-aware simulation
• Knowledge of: Power domains & power states
• Reset vs power interactions
• Strong debug skills across RTL, UPF, and testbench
• ACADEMIC CREDENTIALS
• BE/BTECH or ME/MTECH degree in EE/EECS/CS or equivalent

Additional Information

Additional Information

Axiado is committed to attracting, developing, and retaining the highest caliber talent in a diverse and multifaceted environment. We are headquartered in the heart of Silicon Valley, with access to the world's leading research, technology and talent.

We are building an exceptional team to secure every node on the internet. For us, solving real-world problems takes precedence over purely theoretical problems. As a result, we prefer individuals with persistence, intelligence and high curiosity over pedigree alone. Working hard and smart, continuous learning and mutual support are all part of who we are.

Axiado is an Equal Opportunity Employer. Axiado does not discriminate on the basis of race, religion, color, sex, gender identity, sexual orientation, age, non-disqualifying physical or mental disability, national origin, veteran status or any other basis covered by appropriate law. All employment is decided on the basis of qualifications, merit, and business need.