Senior Staff Physical Design Engineer - STA

Mulya Technologies; Hyderabad; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

Join a pioneering startup as a Senior Staff Physical Design Engineer - STA. You'll work on developing advanced networking silicon and software, utilizing your expertise in static timing analysis to enhance AI compute systems. This role demands proficiency with STA tools and extensive experience in the semiconductor industry.

Qualifications

• 12+ years of experience for BSEE/CE or 10+ years for MSEE/CE.
• Experience with 7nm, 5nm, or 3nm process nodes is a plus.

Responsibilities

• Perform STA at block and full-chip levels.
• Specify and debug timing ECOs.
• Implement hierarchical timing closure methodologies.

Skills

Proficiency with STA tools

Timing constraint verification

High-speed IO timing constraints

Understanding of LVF/OCV variation

Multi-voltage timing convergence

Education

BSEE/CE

MSEE/CE

Tools

Tempus

Tweaker

PrimeTime

Job description

Senior Staff Physical Design Engineer - STA

Join an innovative team at Mulya Technologies as a Senior Staff Physical Design Engineer - STA. We are a startup focused on revolutionizing AI compute systems and infrastructure through the development of advanced networking silicon and software, known as the Accelerated Compute Fabric.

Company Background: Recognized as one of The Information’s 50 Most Promising Startups for 2024, we are driven by a mission to enhance performance and scalability in distributed AI and compute clusters. Our leadership comes from top semiconductor and systems companies, with strong investor backing.

Role Overview: We seek talented engineers experienced in physical implementation of large-scale networking and computing semiconductors, with a focus on static timing analysis. You will work on developing and debugging timing constraints, specifying timing ECOs, and driving timing convergence on complex, high-speed devices.

Responsibilities:

• Perform STA at block and full-chip levels
• Specify and debug timing ECOs
• Perform noise analysis
• Develop and debug timing constraints
• Implement hierarchical timing closure methodologies

Qualifications:

• Proficiency with STA tools like Tempus, Tweaker, PrimeTime
• Experience with timing constraint verification tools is a plus
• Experience with 7nm, 5nm, or 3nm process nodes
• Background in high-speed IO timing constraints (SerDes, DDR)
• Understanding of LVF/OCV variation methodologies
• Knowledge of multi-voltage timing convergence
• BSEE/CE with 12+ years or MSEE/CE with 10+ years of experience

Employment Details:

• Level: Mid-Senior
• Type: Full-time
• Functions: Research, Design, Engineering
• Industries: Hardware Manufacturing, Semiconductor, Network Security

Apply now to join a pioneering company shaping the future of AI infrastructure.