Staff/Senior Staff Physical Design Engineer (Technical Lead)

EnCharge AI; Bengaluru; On-site; INR 2,000,000 - 3,500,000; Full time

Job summary

EnCharge AI is looking for a Staff/Senior Staff Physical Design Engineer (Technical Lead) in Bengaluru, India. This role entails leading a small team while owning the design of critical blocks in our advanced silicon products. You'll ensure the designs meet industry standards and drive optimizations across projects.

The ideal candidate will have extensive experience in physical design and proficiency in advanced tools like Cadence Innovus, backed by a proven record of tape-outs.

Qualifications

• Experience as a Staff/Senior Staff Physical Design Engineer, ideally with multiple successful tape-outs.
• Expertise in Cadence Innovus and proficiency in Tcl and Python scripting.
• Demonstrated ability to optimize PPA for advanced nodes.

Responsibilities

• Lead a team and provide technical direction for physical design engineering.
• Ensure successful delivery of complex sub-chip designs.
• Drive automation efficiencies and manage stakeholder interactions.

Skills

Technical Leadership

PPA Optimization

Automation using Tcl and Python

Stakeholder Management

Tools

Cadence Innovus

Static Timing Analysis (STA)

Job description

Staff/Senior Staff Physical Design Engineer (Technical Lead)

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. EnCharge’s robust and scalable next-generation in-memory computing technology provides orders-of-magnitude higher compute efficiency and density compared to today’s best-in-class solutions. The high-performance architecture is coupled with seamless software integration and will enable the immense potential of AI to be accessible in power, energy, and space constrained applications. EnCharge AI launched in 2022 and is led by veteran technologists with backgrounds in semiconductor design and AI systems.

Job Title: Staff/Senior Staff Physical Design Engineer (Technical Lead)

Experience: Staff 8‑10 years, Senior Staff 11‑13 years

The Role

We are seeking a high-impact Staff/Senior Staff Physical Design Engineer to serve as a Technical Lead for our next-generation silicon products. This is a “player‑coach” role designed for a versatile expert who is equally comfortable architecting a convergence strategy as mentoring a small team of engineers.

You will own the physical delivery of a major sub‑chip or complex block, pushing the absolute limits of PPA (Power, Performance, Area).

As a Staff/Senior Staff lead, you are expected to be the “anchor” of the project—assertive in your decision-making, highly analytical in debugging, and adept at managing stakeholders to ensure we hit our tape‑out milestones without compromise.

Key Responsibilities

• Technical Leadership: Lead a small team of PD engineers, providing technical direction, workload management, and architectural oversight for a sub‑chip or partition.
• Complex Block/Sub‑chip Ownership: Take personal hands‑on ownership of the most critical, high‑congestion, or timing‑critical blocks in the design.
• Timing & PPA Strategy: Act as the primary architect for PD convergence. Derive and implement custom “PPA recipes” that go beyond standard vendor flows to meet aggressive targets.
• Advanced Automation: Drive efficiency across the team by developing sophisticated Tcl and Python scripts for flow automation, data mining, and sign‑off verification.
• Stakeholder Management: Build strong rapport with RTL, DFT, and Synthesis teams. Effectively communicate risks and push for left‑shift optimizations to safeguard the project schedule.
• Sign‑off Accountability: Ensure the sub‑chip meets all gold‑standard sign‑off criteria, including STA, EM/IR (Voltus/Apache), and Physical Verification (Pegasus/Calibre).

Preferred Skills: SOC clocking, FEV/VCLP specialized skills.

Technical Requirements

Experience: Staff 8‑10 years, Senior Staff 11‑13 years. PD experience with a proven track record of multiple successful lead‑level tape‑outs.

Tool Mastery: Expert‑level proficiency in Cadence Innovus/Tempus; deep expertise in Static Timing Analysis (STA), including complex clocking, multi‑corner sign‑off, and crosstalk closure.

PPA Optimization: Demonstrated ability to squeeze performance out of advanced nodes (7nm, 5nm, or below) via custom floorplanning, CTS strategies, and other convergence approaches.

Automation: Advanced scripting in Tcl and Python to build scalable, repeatable design methodologies.

Leadership & Soft Skills

• High workability & assertiveness: Proactive communicator who can hold ground on technical requirements while remaining collaborative and solution‑oriented.
• Analytical problem solver: Identify violations, analyze the root cause, and devise systemic fixes to prevent recurrence.
• Driven & versatile: Possess a senior staff mindset—ready to jump into any part of the flow (from floorplan to GDSII) to unblock the team and meet the schedule.

Mentorship: Passionate about raising the technical bar for the engineers reporting to you.