Staff Design Verification Engineer

SiFive; Hyderabad; On-site; INR 4,000,000 - 6,000,000; Full time

Job summary

SiFive invites a Staff Hardware Engineer in Design Verification to own verification strategy and execute tests for complex OOO processors and cache/memory subsystems.

You will drive test plans from ISA + micro-architecture specs, develop constrained-random UVM testbenches, and build reusable verification components to ensure end-to-end coverage and robust tape-out readiness.

Qualifications

• BS/MS/PhD in EE/CE/CS or related field.
• 8+ years in ASIC/SoC/IP design verification with OOO CPU experience.
• Strong SystemVerilog and UVM expertise.

Responsibilities

• Own verification strategy and test plans for OOO core subsystems.
• Architect constrained-random, coverage-driven UVM testbenches.
• Model ISA/memory behavior for end-to-end checking.
• Write and maintain assertions; apply formal verification.
• Lead debug of complex OOO bugs with RTL teams.

Skills

Leadership

Mentoring DV engineers

Cross-functional collaboration

Debugging complex CPUs

Education

BS/MS/PhD in EE/CE/CS

Tools

SystemVerilog

UVM

OOO verification

Coherence protocols

Job description

About SiFive

As the pioneers who introduced RISC-V to the world, SiFive is transforming the future of compute by bringing the limitless potential of RISC-V to the highest performance and most data-intensive applications in the world. SiFive’s unrivaled compute platforms are continuing to enable leading technology companies around the world to innovate, optimize and deliver the most advanced solutions of tomorrow across every market segment of chip design, including artificial intelligence, machine learning, automotive, data center, mobile, and consumer. With SiFive, the future of RISC-V has no limits.

At SiFive, we are always excited to connect with talented individuals, who are just as passionate about driving innovation and changing the world as we are.

Our constant innovation and ongoing success is down to our amazing teams of incredibly talented people, who collaborate and support each other to come up with truly groundbreaking ideas and solutions. Solutions that will have a huge impact on people’s lives; making the world a better place, one processor at a time.

Are you ready?

To learn more about SiFive’s phenomenal success and to see why we have won theGSA’s prestigious Most Respected Private Company Award(for the fourth time!), check out ourwebsiteandGlassdoorpages.

Job Description:

Summary

As a Staff Hardware Engineer in Design Verification, you will own verification strategy and execution for complex out‑of‑order (OOO) processor and cache/memory subsystems. You will define methodology, lead testplan creation, and drive verification of speculative execution, memory ordering, and coherence features from architecture through tape‑out.

Key Responsibilities

Verification Ownership

• Own verification of OOO core subsystems , e.g.:
• Define verification strategy and test plans from ISA + micro‑architecture specs , with emphasis on:
• Drive coverage closure (functional, code, assertion, and scenario coverage) to sign‑off criteria.

Testbench Architecture & Implementation

• Architect constrained‑random, coverage‑driven UVM testbenches for:
• Develop reusable verification components: generators for OOO stress (back‑to‑back branches, deep speculation, dependency patterns), monitors, scoreboards, and protocol checkers.
• Model reference behavior (ISA / memory model) for end‑to‑end checking of:

Formal & Assertion‑based Verification

• Write and maintain assertions for key OOO properties, e.g.:
• Apply formal verification to targeted units (e.g. ROB, scoreboard, arbiters, FIFOs, coherence controllers, TLB state machines).

Debug & Quality

• Lead debug of complex OOO bugs:
• Work closely with RTL, micro‑architecture, and performance teams to root‑cause issues and refine designs.

Methodology, Infrastructure, and Leadership

• Evolve DV methodology to efficiently cover OOO behavior:
• Mentor junior DV engineers on OOO CPU verification , debug strategies, and best practices.
• Collaborate cross‑functionally with architecture, design, SW, and post‑silicon teams to ensure end‑to‑end coverage of CPU use‑cases and customer workloads.

Required Qualifications:

Education / Experience

• BS/MS/PhD in EE/CE/CS or related field.
• Typically8 + years in ASIC/SoC/IP design verification , with significant experience on out‑of‑order CPU or advanced core projects.

Technical Skills

• Strong expertise in System Verilog and UVM.
• Direct verification experience with OOO CPU micro‑architecture , including several of:
• Solid understanding of:
• Hands‑on experience with:

Preferred / Nice‑to‑Have:

• Experience verifying multi‑core OOO systems and inter‑core coherence.
• Experience with formal verification of OOO structures (e.g. scoreboard, ROB, load‑store queues).
• Exposure to RISC‑V or ARM ISA and privilege specs, including virtualization and security extensions.
• Experience with performance verification or micro‑architectural modeling (to cross‑check pipeline behavior).
• Proven track record of technical leadership on complex CPU or SoC projects (tape‑outs, methodology ownership, cross‑team initiatives).

Additional Information:

This position requires a successful background and reference checks and satisfactory proof of your right to work in:

India

Any offer of employment for this position is also contingent on the Company verifying that you are a authorized for access to export‑controlled technology under applicable export control laws or, if you are not already authorized, our ability to successfully obtain any necessary export license(s) or other approvals.

SiFive is an equal opportunity employer. We celebrate diversity and are committed to creating an inclusive environment for all employees.