Senior SoC PD Lead

Cortex Consultants LLC; Bengaluru Urban; On-site; INR 2,000,000 - 3,500,000; Full time

Job summary

Cortex Consultants LLC is looking for a Senior SoC PD Design professional to lead sophisticated SoC designs in Bengaluru Urban, India. With over 15 years of experience in Digital ASIC architecture, the ideal candidate will engage in technical discussions, ensuring the best quality and performance standards in collaboration with global teams.

The role focuses on advanced semiconductor nodes and includes responsibilities such as capturing design requirements and supporting customer interactions. Candidates should hold a Master's or PhD in Electrical Engineering and possess strong knowledge in SoC PD flows.

Qualifications

• Minimum 15 years of experience in Digital ASIC architecture.
• Profound knowledge in advanced technology nodes such as 8nm, 5nm, 3nm.
• Strong customer-oriented collaboration skills.

Responsibilities

• Capture physical design requirements for complex SoCs.
• Support technical discussions with customers on requirements.
• Write design constraints while collaborating with teams.

Skills

Digital ASIC architecture

Floorplan and clock plan

P&R flow

DRC and LVS

Timing closure

Communication skills

Education

Master's or PhD in Electrical Engineering

Job description

Job Description

We are seeking a highly accomplished Senior SoC PD Design to drive highly sophisticated SoC designs for our global semiconductor Custom Silicon group. Projects are being executed in advanced semiconductor nodes such as 8nm, 5nm, and 3nm. This role centers on technical vision, engineering depth, and cross-regional collaboration, executed jointly by teams in India and Europe. The ideal candidate is a proven PD leader capable of guiding distributed engineering organizations toward innovation, best-in-class quality, and first-pass silicon success.

You will play a key role in our projects and interact with the design, verification, and physical design team as well as with international customers.

This position offers the opportunity to work on cutting-edge technologies for our highly complex SoC and image pipeline development projects.

Job Details

Full-time. 15+ years of experience. Location: Bangalore / Hyderabad.

Responsibilities

• Capturing the Physical design requirements of complex SoCs while working with SoC Architects, including technical evaluation, interaction with internal and external IP providers to align customer requirements of floorplan, area, design closure, and signoff across a wide spectrum of automotive, industrial, or commercial applications.
• Supporting technical discussions with customers for alignment of requirements, tracking implementation as well as power–performance–area restrictions, and collaborating with architects, design, and PD teams in technical discussions during project acquisition and delivery.
• Writing Physical design requirements and design constraints with our team of architects, design, packaging, and DFT, typically accompanying the complete lifecycle with direct contact to Design, Test, and Packaging teams and close coordination with project management.
• Performing detailed calculations to specify area, utilization, power budgets and supporting performance versus area versus power tradeoffs.
• Collaborating with PDK, Foundry, and design teams to ensure that the ASIC meets the required area and power goals.

Qualifications

• Master's or PhD degree in Electrical Engineering, Electronics Engineering, or comparable.
• Minimum 15 years of experience in Digital ASIC architecture and proficiency in floorplan, clock plan, P&R flow, DRC, LVS, and tapeout signoff.
• Experience working in a customer‑oriented, self‑reliant, reliable, and structured manner while collaborating with international development teams.
• Strong interest in SoC PD flows with embedded AI engines and a desire to improve SoC PD flows.
• Good understanding of advanced technology nodes such as 8nm, 5nm, and 3nm, design partitioning, and timing and signoff closure challenges across different technologies.
• In-depth IP knowledge of floorplan, clocking, design partitions, and timing closure.
• Deep working experience with PDK and Foundry teams is an advantage.
• Knowledge of functional safety (ISO 26262) is an advantage.
• Fluent in English, both written and spoken.
• Excellent written and verbal communication skills.

About You

You are highly motivated, not afraid of taking responsibility, and you are a team player. Beyond excellent problem‑solving and analytical skills, you are an efficient professional who enjoys helping extend the organization for further growth.

Our Company

Tessolve Semiconductors, a venture of Hero Electronics, part of the $5B Hero Group, is a design and test engineering service company providing end‑to‑end solutions from product engineering, software, hardware, wireless, automotive, and embedded solutions. We currently have over 3,800 employees worldwide and maintain a global presence across India, Malaysia, Singapore, USA, UK, Europe, and China.