Sr Design Lead-PD

Tessolve; Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Tessolve in Bengaluru is seeking a Physical Design Engineer to implement complex SoCs and IP blocks, driving floorplanning, placement, CTS, routing, and timing closure to deliver manufacturable designs. You will collaborate closely with RTL, STA, and verification teams to optimize power, address signal integrity, and resolve DRC/LVS issues.

You will perform LVS/DRC checks, support ECOs, and prepare tape-out readiness, using Cadence, Synopsys, and Mentor tools.

Qualifications

• Hands-on experience in physical design implementation for complex SoCs.
• Proficient in CTS, routing strategies, and timing closure methodologies.
• Ability to resolve DRC/LVS issues and optimize power and SI.

Responsibilities

• Implement floorplanning, placement, CTS, routing, and timing closure.
• Optimize power and address signal integrity during implementation.
• Collaborate with RTL, STA, and verification teams for design quality.
• Execute physical verification (LVS/DRC) and drive issue resolution.
• Support ECOs and tape-out readiness using standard EDA tools.

Skills

Floorplanning

Placement

CTS

Routing

Timing closure

Power optimization

Signal integrity

LVS/DRC

Tape-out readiness

Tools

Cadence

Synopsys

Mentor Graphics

Job description

About Us Tessolve offers a unique combination of pre-silicon and post-silicon expertise to provide an efficient turnkey solution for silicon bring-up, and spec to the product. With 3200+ employees worldwide, Tessolve provides a one-stop-shop solution with full-fledged hardware and software capabilities, including its advanced silicon and system testing labs. Tessolve offers a Turnkey ASIC Solution, from design to packaged parts. Tessolve's design services include solutions on advanced process nodes with a healthy eco-system relationship with EDA, IP, and foundries. Our front-end design strengths integrated with the knowledge from the backend flow, allows Tessolve to catch design flaws ahead in the cycle, thus reducing expensive re-design costs, and risks. We actively invest in the R&D center of excellence initiatives such as 5G, mmWave, Silicon photonics, HSIO, HBM/HPI, system-level test, and others. Tessolve also offers end-to-end product design services in the embedded domain from concept to manufacturing under an ODM model with application expertise in Avionics, Automotive, Industrial and Medical segments. Tessolve's Embedded Engineering services enable customers a faster time-to-market through deep domain expertise, innovative ideas, diverse embedded hardware & software services, and built-in infrastructure with world-class lab facilities. Tessolve's clientele includes Tier 1 clients across multiple market segments, 9 of the top 10 semiconductor companies, start-ups, and government entities. We have a global presence over 12 countries with office locations in the United States, India, Singapore, Malaysia, Germany, United Kingdom, Canada, UK, Japan, Taiwan, Philippines, and Test Labs in India, Singapore, Malaysia, Austin, San Jose. For more details, visit https://www.tessolve.com/

Job Overview

A Physical Design Engineer responsible for implementing complex SoCs and IP blocks, driving floorplanning, placement, CTS, routing, and timing closure to deliver manufacturable designs. This role requires strong collaboration with RTL, STA, and verification teams, focusing on power optimization, signal integrity, DRC/LVS resolution, ECO execution, and tape-out readiness within the semiconductor industry.

• Job Designation: Physical Design Engineer

What you'll do

• Implement floorplanning, placement, CTS, routing, and achieve timing closure for complex designs
• Optimize power and address signal integrity and design rule checks throughout implementation
• Collaborate with RTL, static timing analysis, and verification teams to ensure design quality
• Execute physical verification (LVS/DRC) and drive resolution of manufacturing issues
• Support ECO implementation and manage tasks required for successful tape-out
• Use industry-standard EDA tools (Cadence, Synopsys, Mentor) for full PD flow

Who you are

• Skilled in physical implementation for SoCs with strong problem-solving and collaboration skills
• Proficient with CTS, routing strategies, and timing closure methodologies
• Experienced in power optimization techniques and signal integrity mitigation practices
• Comfortable performing DRC/LVS checks and guiding issue resolution to tape-out
• Effective communicator who works well across RTL, STA, and verification teams