Senior Design Verification Engineer

844 Altera Semiconductor Technology India Pvt. Ltd.; New Delhi; Hybrid; INR 800,000 - 1,500,000; Full time

Job summary

844 Altera Semiconductor Technology India Pvt. Ltd. is seeking a Verification Engineer in New Delhi. The role involves designing, developing, and validating software for FPGA acceleration while collaborating with cross-functional teams.

The ideal candidate must have a Bachelor’s or Master's degree in Electrical or Computer Engineering and over 9 years of relevant experience, along with proficiency in SystemVerilog and UVM.

This is a regular position with a focus on automation through Python or Perl scripting.

Qualifications

• 9+ years of experience in ASIC or FPGA design verification.
• Strong hands-on experience developing UVM-based testbenches.
• Proficiency in modern verification methodologies.

Responsibilities

• Collaborate with architects and design engineers on verification strategies.
• Develop and implement test cases for design functionality.
• Execute simulation regressions, debug test failures, and analyze root causes.

Skills

SystemVerilog

UVM

Verilog or VHDL

Python

Perl

Tcl

Education

Bachelor's or Master's degree in Electrical or Computer Engineering

Tools

Simulation and debug tools

Job description

Altera is looking for a talented and driven Verification Engineer to design, develop, validate, and/or debug software abstractions and frameworks for acceleration with FPGAs to support embedded, data center, and communication clients.

Key Responsibilities

• Collaborate with architects and design engineers to understand IP specifications and define comprehensive verification strategies and detailed test plans.
• Develop robust, reusable, and constrained‑random verification environments using SystemVerilog and UVM.
• Create and implement directed and random test cases and test sequences to exercise design functionality and uncover potential bugs.
• Develop verification components, including drivers, monitors, scoreboards, and checkers.
• Utilize SystemVerilog Assertions (SVA) and formal verification methods to enhance bug detection and verify complex properties.
• Execute simulation regressions, debug test failures, analyze root causes, and work with designers to implement corrective measures.
• Define and track functional and code coverage metrics to ensure verification completeness and drive coverage closure.
• Develop automation scripts and infrastructure using languages like Python or Perl to improve verification efficiency and flows.
• Participate in technical reviews of specifications, design documents, and test plans, providing valuable input and feedback.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 9+ years of experience in ASIC or FPGA design verification.
• Expertise in HDL languages such as Verilog or VHDL and HVL such as SystemVerilog.
• Strong hands‑on experience in developing UVM‑based testbenches and verification components.
• Proficiency in modern verification methodologies, including coverage‑driven verification (CDV) and assertion‑based verification (ABV).
• Familiarity with industry‑standard protocols such as AMBA (AXI, ACE, CHI, APB), PCIe, or Ethernet is a plus.
• Experience with simulation and debug tools.
• Strong scripting skills in Python, Perl, or Tcl for automation and data analysis.
• Excellent analytical, problem‑solving, and debugging skills.
• Strong communication skills and the ability to work effectively in a collaborative, cross‑functional team environment.

Job Type: Regular

Shift: Shift 1 (India)

Primary Location: Regus, Madhapur

Additional Locations: Bengaluru, Karnataka, India

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation or any other characteristic protected by local law, regulation or ordinance.