Senior Principal Physical Design Engineer

NXP Semiconductors; Pune District; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

NXP India Pvt. Ltd. (Pune) is seeking a Senior Principal Physical Design Engineer to lead end-to-end physical design for complex SoCs and IP blocks.

You will drive floorplanning, P&R, STA, DRC/LVS, and clock tree optimization while mentoring engineers and refining low-power techniques to meet strict power budgets. The role requires 15+ years of ASIC PD experience, strong EDA and scripting skills, and a track record of successful tape-outs on advanced nodes.

Qualifications

• 15+ years of ASIC physical design experience.
• Tape-outs on advanced process nodes.
• Strong understanding of STA, DRC, LVS, and physical implementation workflows.

Responsibilities

• Lead and execute all aspects of physical design for large-scale digital designs from RTL to GDSII, including floor planning, power planning, place and route, clock tree synthesis, STA, formal verification, DRC, and LVS.
• Drive and optimize design methodologies, flows, and scripts to improve efficiency, turnaround time, and design quality.
• Perform critical path analysis and provide innovative solutions to meet aggressive frequency and power targets.
• Collaborate closely with design, architecture, and verification teams to ensure robust design implementation and resolve complex technical issues.
• Mentor junior and mid-level engineers, providing technical guidance and fostering their growth within the physical design domain.
• Evaluate and integrate new EDA tools and technologies to enhance physical design capabilities.
• Contribute to defining and reviewing design specifications and architecture documents from a physical implementation perspective.
• Develop and implement low-power design techniques (e.g., clock gating, power gating, multi-voltage design) to achieve challenging power budgets.
• Generate comprehensive reports and documentation throughout the design cycle.

Skills

Leadership

Mentoring

Communication

Problem solving

Team collaboration

Scripting (Tcl, Python, Perl)

Education

Bachelor's or Master's in Electrical/Electronics Engineering

Tools

Cadence Innovus/Tempus

Synopsys Fusion Compiler/PrimeTime

Ansys RedHawk/PathFinder

Job description

Company:** NXP India Pvt. Ltd. (Pune)

Job Summary

As a Senior Principal Physical Design Engineer, you will be a key technical leader responsible for driving and executing advanced physical design activities for complex SoC and IP blocks. You will play a pivotal role in achieving challenging performance, power, and area targets for cutting-edge semiconductor products.

Job Responsibilities

• Lead and execute all aspects of physical design for large-scale digital designs from RTL to GDSII, including floor planning, power planning, place and route, clock tree synthesis, static timing analysis (STA), formal verification, design rule checking (DRC), and layout versus schematic (LVS).
• Drive and optimize design methodologies, flows, and scripts to improve efficiency, turnaround time, and design quality.
• Perform critical path analysis and provide innovative solutions to meet aggressive frequency and power targets.
• Collaborate closely with design, architecture, and verification teams to ensure robust design implementation and resolve complex technical issues.
• Mentor junior and mid-level engineers, providing technical guidance and fostering their growth within the physical design domain.
• Evaluate and integrate new EDA tools and technologies to enhance physical design capabilities.
• Contribute to defining and reviewing design specifications and architecture documents from a physical implementation perspective.
• Develop and implement low-power design techniques (e.g., clock gating, power gating, multi-voltage design) to achieve challenging power budgets.
• Generate comprehensive reports and documentation throughout the design cycle.

Job Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Electronics Engineering, or a related field.
• 15+ years of extensive experience in ASIC physical design with a strong track record of successful tape-outs on advanced process nodes.
• Deep expertise in industry-standard EDA tools for physical design (e.g., Cadence Innovus/Tempus, Synopsys Fusion Compiler/PrimeTime, Ansys RedHawk/PathFinder).
• Proficiency in scripting languages (Tcl, Perl, Python) for automation and flow development.
• Strong understanding of static timing analysis concepts, constraints, and methodologies.
• Hands-on experience with low-power design techniques and methodologies.
• Solid understanding of semiconductor physics, process technology, and DFM (Design for Manufacturability) principles.
• Demonstrated ability to lead technical initiatives and mentor other engineers.
• Excellent problem-solving, analytical, and communication skills.
• Ability to work effectively in a fast-paced, collaborative team environment.

More information about NXP in India... #LI-7013 NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com

Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills.

Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress.

Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.

Thank you for your understanding.