Physical Design Methodology Lead

NXP Semiconductors; Dadri; On-site; INR 5,000,000 - 6,800,000; Full time

Job summary

NXP Semiconductors in India seeks a senior Flow and Methodology Engineer to lead backend RTL-to-GDS flows for advanced SoC/ASIC designs. You will drive throughput, quality, and reliability by advancing tapeout-ready methodologies across synthesis, floorplanning, place and route, CTS, and signoff processes.

The role requires deep expertise in physical design flows, extensive scripting ability, and collaboration with cross-functional teams to deliver robust, scalable production flows.

Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline.
• Typically 15+ years of experience in physical design, backend implementation, CAD, design automation, or flow and methodology development for ASIC or SoC products.
• Deep hands-on expertise with RTL-to-GDS implementation flows, including synthesis, floorplanning, placement, CTS, routing, optimization, extraction, timing closure, ECO, and physical verification.

Responsibilities

• Own and continuously improve backend RTL-to-GDS implementation flows for advanced process nodes, emphasizing quality, scalability, and designer productivity.
• Lead methodology development across CTS, timing closure, congestion analysis, and signoff readiness; collaborate with design, verification, DFT, and signoff teams.
• Promote automation-first thinking with scripting, regression systems, data-driven flow analysis, and operator dashboards.

Skills

RTL-to-GDS flows

Scripting

EDA tools

Power/Timing analysis

Education

Bachelor's or Master's in Electrical/Computer Engineering/CS

Tools

Synopsys

Cadence

Siemens EDA

Job description

Role Overview

We are seeking a senior-level Flow and Methodology Engineer to lead backend design automation for advanced process node SoC and ASIC implementation. This role focuses on enabling robust, scalable, and production-ready RTL-to-GDS flows across synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, power grid implementation, extraction, physical verification, and signoff closure. The ideal candidate will combine deep technical expertise in physical design methodology with the ability to drive initiatives from concept definition through validation, deployment, and sustained production support.

Key Responsibilities

Own, develop, and continuously improve backend RTL-to-GDS implementation flows for advanced process nodes, with emphasis on quality of results, scalability, runtime, and designer productivity. Drive methodology development across place and route, CTS, timing closure, congestion analysis, ECO implementation, power grid design, IR/EM analysis, extraction, and signoff readiness. Partner with design, architecture, DFT, verification, timing, low-power, package, foundry, and signoff teams to ensure flows meet tapeout requirements for complex SoC and IP programs. Lead initiatives from concept and feasibility assessment through prototype development, benchmarking, validation, documentation, deployment, training, and production support. Establish repeatable best practices, reference flows, automation frameworks, dashboards, and metrics to improve PPA, reduce turnaround time, and improve predictability across projects. Work closely with EDA vendors to evaluate, enable, and adopt the latest technologies in physical implementation, signoff, power integrity, machine learning optimization, and agentic/AI-assisted design automation. Conduct competitive benchmarking and technology evaluations to identify flow gaps, quantify benefits, and influence vendor roadmaps. Debug complex flow, tool, constraint, timing, power, congestion, and physical verification issues, and provide expert guidance to design implementation teams. Promote automation-first thinking through scripting, reusable infrastructure, regression systems, data-driven flow analysis, and intelligent decision support. Provide deployment support, training, and hands-on technical leadership to ensure new methodologies are adopted effectively across engineering teams.

Required Qualifications

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline. Typically 15+ years of experience in physical design, backend implementation, CAD, design automation, or flow and methodology development for ASIC or SoC products. Strong hands-on expertise with RTL-to-GDS implementation flows, including synthesis, floorplanning, placement, CTS, routing, optimization, extraction, timing closure, ECO, and physical verification. Deep understanding of timing signoff, constraints, STA debug, SDC methodology, multi-corner multi-mode closure, setup/hold optimization, and correlation across implementation and signoff tools. Experience with power grid design, IR drop, EM analysis, low-power implementation, multi-voltage design, UPF-based flows, and power optimization techniques. Proven ability to improve PPA through methodology innovation, tool tuning, automation, and cross-functional problem solving. Strong scripting and automation skills using Tcl, Python, Perl, shell scripting, or equivalent technologies. Experience working with leading EDA platforms from vendors such as Synopsys, Cadence, Siemens EDA, or equivalent tool ecosystems. Demonstrated ability to influence technical direction, communicate complex topics clearly, and drive cross-team initiatives to closure.

About NXP

More information about NXP in India... #LI-2734 NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills. Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality. Thank you for considering a career at NXP. To help you prepare for the different steps in our hiring process, see the following useful advice and tips. Thank you for your understanding.

Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities. Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited. Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise.