Sr Design Engineer

NXP Semiconductors; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

NXP Semiconductors in India is seeking an IO circuit design engineer to craft GPIO LVDS, LVCMOS, SSTL, HSTL, and DDR interfaces, along with high-speed SerDes support. You will perform transistor-level design and advanced simulations, guiding layout reviews with the physical design team.

Minimum 2–4 years in Analog/Mixed-Signal or IO design, Cadence Virtuoso, and SPICE tools are essential. The role involves silicon bring-up, characterization, and working across system, package, reliability, and

Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.
• 2-4 years of experience in Analog/Mixed-Signal or IO Circuit Design.
• Hands-on design and simulation using Cadence Virtuoso and SPICE-based tools.

Responsibilities

• Design and develop custom IO circuits including GPIO LVDS LVCMOS SSTL HSTL DDR interfaces and high-speed SerDes support.
• Perform transistor-level design and simulation using advanced CMOS nodes.
• Conduct pre-layout and post-layout simulations for timing, power, and reliability.
• Drive layout reviews and collaborate with physical design teams to meet targets.
• Support silicon bring-up, characterization, debugging, and production ramp activities.

Skills

IO circuit design

Analog/mixed-signal

Transistor-level design

Signal integrity

Mentoring juniors

Education

Bachelor's or Master's in Electronics / Electrical / Microelectronics

Tools

Cadence Virtuoso

SPICE simulators (Spectre/HSPICE/FineSim)

LVS/DRC/EMIR checks

IBIS/IBIS-AMI modeling

Job description

Key Responsibilities

• Design and develop custom IO circuits including: GPIO LVDS LVCMOS SSTL HSTL DDR Interfaces High-speed SerDes support circuits
• Perform transistor-level design and simulation using advanced CMOS technology nodes.
• Develop and optimize: ESD protection circuits Level shifters Input buffers Output drivers On-chip termination circuits
• Conduct pre-layout and post-layout simulations for functionality, timing, power, noise, and reliability.
• Perform signal integrity analysis including: IBIS model generation Package-aware simulations Crosstalk and reflection analysis
• Drive layout reviews and work closely with physical design teams to ensure design quality and performance targets.
• Support silicon bring-up, characterization, debugging, and production ramp activities.
• Collaborate with system, package, reliability, and product engineering teams.
• Develop and maintain design documentation, specifications, and verification reports.

Required Qualifications

• Bachelor's or Master's degree in Electronics Engineering, Electrical Engineering, Microelectronics, or related field.
• 2-4 years of experience in Analog/Mixed-Signal or IO Circuit Design.
• Strong understanding of: CMOS device physics Analog circuit design fundamentals IO architectures and standards ESD design methodologies.
• Hands-on experience in custom circuit design using Cadence Virtuoso.
• Expertise in SPICE-based simulators such as Spectre, HSPICE, or FineSim.
• Experience with advanced technology nodes (16nm/7nm/5nm preferred).
• Good knowledge of LVS, DRC, EMIR, and reliability checks.
• Familiarity with process corners, Monte Carlo analysis, and yield optimization techniques.

Preferred Skills

• Experience with DDR4/DDR5, LPDDR, USB, PCIe, MIPI, or Ethernet interfaces.
• Knowledge of package modeling and SI/PI analysis tools.
• Understanding of ESD standards such as HBM, CDM, and IEC.
• Experience in silicon validation and lab characterization.
• Scripting skills in Python, Perl, Tcl, or SKILL.
• Familiarity with IBIS and IBIS-AMI model generation.

Desired Competencies

• Strong analytical and debugging skills.
• Excellent communication and cross-functional collaboration.
• Ability to lead technical discussions and mentor junior engineers.
• Proven track record of delivering silicon successfully from specification to production.
• Self-driven with strong problem-solving abilities.
• Nice to Have Experience in automotive, AI/ML, networking, mobile, or data center SoCs.
• Exposure to functional safety and reliability requirements.
• Prior ownership of complete IO IP development cycle.

This role is ideal for an engineer who has hands-on experience in IO circuit design, ESD, signal integrity, and silicon validation, and is looking to contribute to next-generation semiconductor products.

More information about NXP in India... #LI-7013 NXP Semiconductors N.V. (NASDAQ: NXPI) enables a smarter, safer, and more sustainable world through innovation. As the world leader in secure connectivity solutions for embedded applications, NXP is pushing boundaries in the automotive, industrial & IoT, mobile, and communication infrastructure markets. For more information, visit www.nxp.com Bright Minds. Bright Futures. We believe that a key component to growing our business is to develop our people. To enable you to grow your career at NXP, we offer online and offline learning opportunities to help you develop some of your core and professional skills. Commitment At NXP. We recognize NXP is a powerful change agent as we continue to deliver innovative solutions that advance a more sustainable future. We remain steadfast in our commitment to sustainability and making measurable year-on-year progress. Also, we aim to create an inclusive work environment and we will not tolerate racism, discrimination or harassment of any kind. We have programs in place focused on diversity, inclusion and equality.

Thank you for considering a career at NXP.

Please note that NXP operates under a strict Preferred Supplier List (PSL) for all recruitment activities. Any candidate profiles or resume submitted without a prior written agreement or explicit request from our Talent Acquisition team will be considered unsolicited. Such submissions will be deemed free of any obligations, and no fees will be paid by NXP or any of its affiliates, subsidiaries, or divisions - regardless of whether the candidate is hired, either coincidentally or otherwise. Thank you for your understanding.