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Avecas Technologies is seeking a Senior Physical Design Engineer to lead the PD implementation for FinFET designs at 7nm/5nm. The role requires hands-on experience with floorplanning, placement, CTS, routing, and timing closure.
Collaboration with design and DFT teams is essential to ensure successful tapeouts. The position is full-time and based in Bangalore, with an emphasis on delivering high-performance VLSI solutions across advanced nodes.
Bangalore Avecas Technologies Physical Design 8+ yrs Full-time
Lead PD implementation for FinFET designs including floorplanning, placement, CTS, routing, and timing closure at 7nm/5nm. Collaborate with design and DFT teams for tapeout.
Innovus ICC2 PrimeTime Floorplanning CTS Routing FinFET UPF
Domain
Physical Design
Location
Type
Full-time
Posted
Delivering VLSI excellence from five strategic locations worldwide
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