Physical Design Engineer

VeriFast Technologies; Ahmedabad District; On-site; INR 4,000,000 - 6,500,000; Full time

Job summary

VeriFast Technologies is seeking a Senior Physical Design Engineer with 7+ years of hands-on experience in ASIC/SoC physical design. You will own RTL-to-GDS flows, drive timing closure, and lead block-level floorplanning, CTS, routing, and signoff in a fast-paced environment.

The role requires expertise in advanced nodes (TSMC 7nm/5nm/3nm) and a track record of multiple tapeouts. Collaboration with STA, DFT, and Signoff teams will be essential to ensure schedule‑critical closure and high-quality

Qualifications

• 7+ years of hands-on experience in ASIC/SoC Physical Design.
• Strong RTL-to-GDS / RTL-to-GDSII physical implementation flow experience.
• Hands-on with advanced technology nodes, preferably 7nm/5nm/3nm.
• At least 3 successful tapeouts highly preferred.
• Solid understanding of floorplanning, power planning, synthesis, placement, CTS, routing, and physical optimization.
• Experience with DRC, LVS, ANT, EMIR, and physical signoff.

Responsibilities

• Own complex ASIC/SoC blocks through RTL-to-GDS physical implementation flow.
• Perform block-level floorplanning, power planning, synthesis, placement, CTS, routing, and physical optimization.
• Drive timing closure, STA, ECO implementation, power, area, congestion, and routability optimization.
• Lead DRC, LVS, ANT, EMIR, and other physical verification signoff activities.
• Conduct EM/IR analysis and push issues to closure.
• Provide RTL and routability feedback to full-chip stakeholders.
• Support block integration, hierarchical implementation, and full-chip assembly.
• Collaborate with STA, Power Integrity, DFT, Physical Verification, RTL, Architecture, and Signoff teams.

Skills

RTL-to-GDS flows

Timing closure

Power optimization

EM/IR analysis

Floorplanning

Synthesis

Routing

Block-level implementation

Cross-functional collaboration

Debugging complex timing issues

Education

Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field

Tools

Synopsys

Cadence

Siemens EDA

Job description

Job Title: Physical Design Engineer (7+ Years)

Location: Ahmedabad, Gujarat

About the Role:

VeriFast Technologies is looking for an experienced Physical Design Engineer with 7+ years of hands‑on experience in ASIC/SoC physical implementation and RTL-to-GDS (RT2GDS) flows.

The ideal candidate should have strong expertise in advanced technology nodes, physical implementation, timing closure, power optimization, and physical signoff. Candidates with 3+ successful tapeouts on advanced nodes such as TSMC 7nm, 5nm, or 3nm will be highly preferred.

Key Responsibilities:

• Own complex ASIC/SoC blocks through the complete RTL-to-GDS physical implementation flow.
• Perform block‑level floorplanning, power planning, synthesis, placement, CTS, routing, and physical optimization.
• Drive timing closure, STA, ECO implementation, power, area, congestion, and routability optimization.
• Perform and drive closure of DRC, LVS, ANT, and other physical verification signoff activities.
• Perform EM/IR (EMIR) analysis and drive issues to closure.
• Analyze implementation challenges and provide RTL and routability feedback to full‑chip design stakeholders.
• Identify physical implementation risks proactively and recommend design changes to avoid schedule‑critical closure issues.
• Support block integration, hierarchical implementation, and full‑chip assembly.
• Collaborate with STA, Power Integrity, DFT, Physical Verification, RTL, Architecture, and Signoff teams.
• Debug and resolve complex timing, congestion, clocking, power, routing, and physical design issues.
• Contribute to improving physical design methodologies, flows, and implementation quality.
• Mentor junior engineers while remaining highly hands‑on with physical implementation activities.

Required Qualifications

• Bachelor's or Master's degree in Electronics, Electrical Engineering, VLSI, or a related field.
• 7+ years of hands‑on experience in ASIC/SoC Physical Design.
• Strong experience in RTL-to-GDS / RTL-to-GDSII physical implementation flows.
• Hands‑on experience with advanced technology nodes, preferably TSMC 7nm / 5nm / 3nm.
• Experience with at least 3 successful tapeouts is highly preferred.
• Strong understanding of:
• Floorplanning
• Power planning
• Synthesis
• Placement
• Clock Tree Synthesis (CTS)
• Routing
• Physical optimization
• ECO implementation
• Static Timing Analysis (STA)
• Timing closure
• Power and area optimization
• Congestion and routability analysis
• Hands‑on experience with DRC, LVS, Antenna (ANT), EMIR, and physical signoff.
• Strong debugging and problem‑solving skills.
• Good communication and cross‑functional collaboration skills.

Preferred Skills:

• Experience working on complex ASIC/SoC designs and hierarchical implementation.
• Strong understanding of full‑chip physical design and block‑level implementation.
• Experience with advanced‑node physical design challenges.
• Ability to analyze timing, congestion, power, routing, and physical verification issues and drive them to closure.
• Experience working with industry‑standard EDA tools from Synopsys, Cadence, or Siemens EDA.
• Experience mentoring engineers and contributing to physical design flow/methodology improvements.

Why Join VeriFast Technologies?

• Work on next‑generation ASIC and SoC physical design programs.
• Opportunity to work on advanced semiconductor technologies and complex designs.
• Collaborate with experienced physical design, RTL, STA, DFT, and signoff teams.
• Work on challenging timing, power, area, congestion, and physical signoff problems.
• Be part of a fast‑growing semiconductor technology company with strong technical challenges and career growth opportunities.
• Competitive compensation and opportunities for continuous learning and professional growth.