Senior Physical Design and Implementation Engineer - GPU

Google India Pvt Ltd; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Google India Pvt Ltd is seeking a Senior Physical Design and Implementation Engineer for GPU teams to push the boundaries of custom silicon. You will lead PPA-driven RTL2GDS implementation from synthesis through sign-off, collaborating with multi-disciplinary teams to meet power, performance, and area goals.

The role demands deep expertise in physical design and a track record of chip tape-outs. Join a team that powers Google's direct-to-consumer products and contribute to cutting-edge hardware

Qualifications

• Bachelor's degree in a related field and 8 years of physical design experience with participation in 4 chip tape-outs.
• Master's or PhD preferred with emphasis on computer architecture.
• Experience with scripting languages (Perl, Python, TCL) is desirable.

Responsibilities

• Use analytical and simulation techniques to ensure Performance, Power, and Area (PPA) targets are met and oversee ASIC RTL2GDS implementation for high PPA designs.
• Collaborate with cross-functional teams to debug failures or performance shortfalls in lab or simulations.
• Design chips, chip-subsystems, or partitions from synthesis through place & route and sign-off convergence to meet architecture goals of power, performance, and area.
• Develop, validate, and improve EDA methodologies to enable cross-functional teams to build blocks that are correct by construction.
• Manage block and full-chip level physical implementation and QoR (power, timing, area).

Education

Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related field

Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science

Tools

Perl

Python

TCL

Job description

Physical Design and Implementation Engineer, GPU

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
• 8 years of experience in physical design and participation in 4 chip tape outs.

Preferred qualifications:

• Master's degree or PhD in Electrical Engineering, Computer Engineering or Computer Science, with an emphasis on computer architecture.
• Experience with scripting languages such as Perl, Python, or TCL.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

Responsibilities

• Use analytical and simulation techniques to ensure Performance, Power, and Area (PPA) is within defined requirements and develop all aspects of ASIC RTL2GDS implementation for high PPA designs.
• Collaborate with cross-functional teams to debug failures or performance shortfalls program goals in lab or simulation.
• Design chips, chip-subsystems, or partitions within subsystems from synthesis through place and route and sign off convergence, ensuring that the design meets the architecture goals of power, performance, and area.
• Develop, validate, and improve Electronic Design Automation (EDA) methodology for a specialized sign off or implementation domain to enable cross-functional teams to build and deliver blocks that are correct by construction and ease convergence efforts.
• Manage block and full-chip level physical implementation and QoR (power, timing, area).

Experience Level

Senior Level