Senior/Lead/Physical Design Engineer

Thinsil Technologies; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Thinsil Technologies in Bengaluru is seeking a Senior/Lead Physical Design Engineer to own end-to-end physical design from floorplanning to tape-out for ASIC/SoC projects.

You will lead block-level or full-chip PD efforts, drive timing closure, PPA optimization, and sign-off while mentoring junior engineers and collaborating with RTL, STA, DFT teams. Proficiency with ICC2, Innovus, PrimeTime, Fusion Compiler or Tempus and scripting in TCL/Python is essential.

Qualifications

• Experience leading block-level or full-chip physical design projects through tape-outs.
• Strong hands-on experience across the complete Physical Design flow from floorplanning to signoff.
• Expertise in timing closure, PPA optimization, and physical verification.

Responsibilities

• Lead complete physical design implementation, collaborating with RTL, STA, DFT and cross-functional teams.
• Drive timing closure, congestion, power, IR drops and signal integrity to meet aggressive project timelines.
• Mentor engineers, influence design methodologies, and push for quality and execution excellence.

Skills

PD design

Timing closure

PPA optimization

ICC2

Innovus

PrimeTime

Scripting (TCL/Python)

Mentoring

Collaboration

Full-chip/Block-level

Education

Bachelor's/Master's in Electronics or ECE

Tools

ICC2

Innovus

PrimeTime

Fusion Compiler

Tempus

Job description

Role & responsibilities

we are looking for an experienced Senior/Lead Physical Design Engineer who is passionate about delivering high-quality ASIC/SoC designs and enjoys taking ownership from floorplanning to tape-out. In this role, youll lead the complete physical design implementation, working closely with RTL, STA, DFT, and other cross-functional teams to achieve the best PPA while meeting aggressive project timelines. You should be comfortable handling complex blocks independently, driving timing closure, resolving congestion, power, IR/EM, and signal integrity challenges, and ensuring signoff quality. Beyond technical expertise, were looking for someone who enjoys mentoring engineers, influencing design methodologies, and fostering a collaborative team environment. A strong understanding of advanced technology nodes, hands-on experience with industry-standard EDA tools such as ICC2, Innovus, PrimeTime, Fusion Compiler, or Tempus, along with scripting skills in TCL, Python, or Perl, are essential. The ideal candidate is a proactive problem solver with strong technical leadership, excellent communication skills, and a track record of delivering successful tape-outs while driving quality, innovation, and execution excellence.

Qualification & skills:

• Bachelors or Masters degree in Electronics, Electrical Engineering, VLSI, or a related field.
• Proven experience leading block-level or full-chip physical design projects through successful tape-outs.
• Strong hands-on experience across the complete Physical Design flow from floorplanning to signoff.
• Expertise in timing closure, PPA optimization, and physical verification.
• Experience with advanced technology nodes and industry-standard Physical Design tools.
• Proficiency in TCL, Python, or Shell scripting.
• Strong problem-solving, collaboration, and mentoring skills with the ability to drive projects independently.