Senior Lead FPGA Verification Engineer - Actuation Systems M/F

Safran Group

Bengaluru

On-site

INR 3,500,000 - 7,000,000

Full time

14 days+

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Job summary

Safran in Bengaluru seeks a Senior Lead FPGA Verification Engineer for Actuation Systems. You will verify FPGA designs using SystemVerilog/UVM in a DO-254 framework, develop test environments, and lead junior engineers while collaborating with design teams.

The role requires hands-on SV-UVM experience, proficiency with simulators like Questa/Modelsim, and strong debugging. Location: Kundalahalli, Bangalore, India.

Qualifications

Bachelor's or Master’s degree in Engineering (ECE or VLSI).
7–11 years of industry experience in ASIC/FPGA development, integration and verification.
Hands-on experience creating SV-UVM environments from scratch.
Hands-on experience with Questa or Modelsim or similar simulators.
Experience with DO-254 verification processes.
RTL design experience using VHDL is a plus.
Experience with DOORS/Jama is a plus and leadership for juniors.
Strong team leadership and progress reporting skills.
Excellent oral and written communication.

Responsibilities

Develop an effective suite of tests and test environments using SystemVerilog UVM.
Create test plans and self-checking benches to meet verification criteria and coverage.
Participate in requirement validation and reviews.
Work with protocols PCIe, SPI, ARINC 429, Mil-1553, and image processing.
Collaborate with design teams to develop verification architecture and plans.
Develop verification environment from scratch for block and system level.
Coordinate with design to address debug and coverage gaps.
Drive functional and structural coverage closure for modules and systems.
Leverage languages like SystemVerilog/UVM and Perl for automation.
Identify root causes and provide strong debugging analysis.
Provide technical guidance to junior engineers on verification tasks.

Skills

SystemVerilog

UVM

Debugging

Scripting

Education

Bachelor's or Master's in Engineering (ECE or VLSI)

Tools

Questa

Modelsim

DOORS/Jama

Job description

Senior Lead FPGA Verification Engineer - Actuation Systems M/F

Vacancy details

General information

Entity

Safran is an international high-technology group operating in the fields of aerospace (propulsion, equipment and interiors), space and defense. Its mission is to contribute sustainably to a safer world, where air transport becomes ever more environmentally friendly, comfortable and accessible. Present on every continent, the Group employs 110,000 people and generated €31.3 billion in revenue in 2025. Safran holds, either independently or through partnerships, leading global or European positions in its markets.

Safran was ranked second in the Aerospace & Defense sector in TIME magazine's "World's Best Companies 2025" ranking.

Safran Electronics & Defense is an international company with more than 19,000 employees who bring together expertise and team spirit to design high-technology solutions for the aerospace, defense and space sectors. By combining human and technological intelligence, the company develops products and services for both civil and military customers, operating on land, at sea, in the air and in space.

Reference

2026-171190

Position description

Domain

Research, design and development

Job field / Job profile

Electronics and automation - FPGA

Job title

Senior Lead FPGA Verification Engineer - Actuation Systems M/F

Employment type

Permanent

Part time / Full time

Full-time

Job description

Description of the Role:

In this role as a Senior Lead Engineer (FPGA Verification Engineer, Actuation Systems) actively contribute towards Requirement-Based Testing (RBT) in FPGA verification using System Verilog and UVM methodology, in accordance to DO-254 process.

Primary Responsibilities:

1.Develop an effective suite of tests and test environments using System Verilog UVM, based tests to achieve predefined requirement verification goals.

2.Develop test-plan, self-checking test-benches to meet the verification criteria and code coverage.

3.Participate in requirement validation and requirement review.

4.Protocols – PCIe, SPI, ARINC 429, Mil 1553, Image processing.

5.Actively participate in a team environment and work independently with design teams to develop verification architecture, applications, comprehensive test plans and address issues.

6.Verification environment development from scratch for block level and system level.

7.Work closely with design team on design de-bugging, coverage gap analysis etc.

8.Independently work towards functional and structural coverage closure for module and system level designs.

9.Advanced skills in various programming languages such as System Verilog/UVM, PERL or any scripting language.

10.Apply techniques and skills required to identify a root cause of a given issue and very good debugging skills.

11.Technical guidance to the junior engineers on verification tasks.

Candidate skills & requirements

Qualifications:

Bachelor's/Master's degree in Engineering (ECE or VLSI)

7-11 years of Industry experience with experience in development, integration & verification of ASIC/FPGA.

Hands on experience in developing SV-UVM verification environment from scratch.

Hands on experience with Questa or Modelsim or similar advanced simulation tools.

Hands on experience in DO-254 verification process.

Hands on experience in developing UVM verification environment from scratch from scratch with stimulus to achieve the code coverage, robust testing of the designs independently.