Greetings from Thales India Pvt Ltd.....!
Job Title: -Senior Engineer/Tech Lead - FPGA Verification (VHDL & DO-254)
Position Overview
The Thales India Engineering Competency Center (ECC) is seeking a Hands-on FPGA Engineer to perform complex verification activities using VHDL to meet the DO-254 excellence.
Qualifications
Experience: 5+ years in FPGA Verification.
Industry: Aerospace or Defense background would be an added advantage.
Education: B.Tech/B.E or M.Tech/Masters in Electronics & Communication
Required Skills:
Key Responsibilities:
1. Operational Execution
- Environment Development: Directly architect and code critical VHDL environment including BFMs/Models and complex test scenarios.
- Complex Interfaces Validation: Experience in verification of communication interfaces and bus standards (Example: AXI4, SPI, PCIe, UART, ARINC, 818/664 )
- Problem Solving: Take the lead on the most challenging technical bottlenecks, from simulation mismatches to physical hardware-software integration issues.
- Skill Uplift: Adoption of latest tools, use of AI.
2. Certification & Delivery (DO-254)
- End-to-End Ownership: Be accountable for the full verification of assigned function/block, ensuring 100% traceability between requirements and test results.
- Artifact Production: Hands-on drafting and self/peer review of critical certification documents (Hardware Requirement Specification, Hardware Verification Test procedure & Results document, etc.)
Critical Competencies :
- Expert VHDL (Active Practitioner): Current, hands-on experience in defining verification architectures and building verification environments.
- Advanced Protocols: Deep technical knowledge of AXI4, PCIe, Ethernet, UART, and ARINC standards.
- Process Assurance: DO-254 (DAL A/B) or comparable safety standards.
- Tool Mastery: Advanced user of Siemens-Questasim/Synopsys-VCS/Cadence-Xcelium/Rivera-PRO.
- Automation: Capable of developing Python/TCL scripts to optimize the verification flow.
- Project Stewardship: Ability to execute projects within planned timelines.