Senior Layout Engineer

ON Semiconductor; Bengaluru; Vor Ort; INR 600.000 - 1.200.000; Vollzeit

Zusammenfassung

ON Semiconductor is seeking a motivated Analog Layout Engineer with hands-on experience in custom analog and mixed-signal layout development. You will apply matching techniques, guard rings, shielding, and DNW-based layouts to deliver robust designs.

Collaborating with circuit designers, you will verify layouts through DRC/LVS/ERC sign-off and support extraction and post-layout verification activities. 2–3 years of relevant experience required.

Qualifikationen

• B.E. in Electronics, E&TC or a relevant field.
• 2-3 years of hands-on analog/custom layout experience.
• Strong understanding of device matching, common centroid layouts, interdigitization, guard rings and shielding, latch-up prevention concepts, and analog routing methodologies.
• Familiarity with semiconductor process technology and device cross-sections; DNW experience preferred.
• Strong debugging skills in DRC/LVS verification and good analytical problem-solving abilities.
• Experience with Cadence Virtuoso and standard verification flows.
• Good communication and teamwork skills.

Aufgaben

• Develop high-quality custom analog and mixed-signal layouts from schematics.
• Implement device matching, common-centroid structures, shielding, guard rings, symmetry, and parasitic-aware layout techniques.
• Perform layout verification and achieve clean DRC, LVS, and ERC sign-off.
• Debug DRC/LVS issues independently and drive closure efficiently.
• Understand process cross-sections, layer interactions, and device structures.
• Work with circuit designers to ensure proper implementation of design intent.
• Participate in layout reviews and incorporate feedback for quality improvements.
• Support extraction and post-layout verification activities.

Kenntnisse

Analog layout expertise

Device matching techniques

Common centroid layouts

Interdigitization

Guard rings and shielding

Latch-up prevention

Analog routing

Cadence Virtuoso

DRC/LVS/ERC debugging

Teamwork and communication

Ausbildung

B.E. in Electronics or E&TC or relevant field

Tools

Cadence Virtuoso

Jobbeschreibung

Job Summary

We are seeking a motivated Analog Layout Engineer with strong hands‑on experience in custom analog and mixed-signal layout development. The candidate should have a solid understanding of analog layout fundamentals, matching techniques, process understanding, and verification closure. Experience in higher-node technologies and DNW-based layouts is preferred.

Key Responsibilities

• Develop high-quality custom analog and mixed-signal layouts from schematics.
• Implement device matching, common-centroid structures, shielding, guard rings, symmetry, and parasitic‑aware layout techniques.
• Perform layout verification and achieve clean DRC, LVS, and ERC sign‑off.
• Debug DRC/LVS issues independently and drive closure efficiently.
• Understand and interpret process cross‑sections, layer interactions, and device structures.
• Work closely with circuit designers to ensure proper implementation of design intent.
• Participate in layout reviews and incorporate feedback for quality improvements.
• Support extraction and post‑layout verification activities.

Required Skills

• B.E (Electronics, E&TC or relevant field)
• 2-3 years of hands‑on analog/custom layout experience.
• Strong understanding of:
  • Device matching techniques
  • Common centroid layouts
  • Interdigitization
  • Guard rings and shielding
  • Latch‑up prevention concepts
  • Analog routing methodologies
• Good understanding of semiconductor process technology and device cross‑sections.
• Experience with Deep N-Well (DNW) processes is preferred.
• Strong debugging skills in DRC/LVS verification.
• Good, logical reasoning and analytical problem‑solving skills.
• Familiarity with Cadence Virtuoso and industry-standard verification flows.
• Good communication and teamwork skills.

Job Summary

We are seeking a motivated Analog Layout Engineer with strong hands‑on experience in custom analog and mixed-signal layout development. The candidate should have a solid understanding of analog layout fundamentals, matching techniques, process understanding, and verification closure. Experience in higher-node technologies and DNW-based layouts is preferred.

Key Responsibilities

• Develop high-quality custom analog and mixed-signal layouts from schematics.
• Implement device matching, common-centroid structures, shielding, guard rings, symmetry, and parasitic‑aware layout techniques.
• Perform layout verification and achieve clean DRC, LVS, and ERC sign‑off.
• Debug DRC/LVS issues independently and drive closure efficiently.
• Understand and interpret process cross‑sections, layer interactions, and device structures.
• Work closely with circuit designers to ensure proper implementation of design intent.
• Participate in layout reviews and incorporate feedback for quality improvements.
• Support extraction and post‑layout verification activities.

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