Senior Analog Layout Engineer

Sasken Technologies Limited; Bengaluru; Vor Ort; INR 900.000 - 1.300.000; Vollzeit

Zusammenfassung

Sasken Technologies Limited seeks an experienced Analog Layout Engineer to deliver robust analog, mixed-signal, and high-speed layouts for advanced CMOS technologies. You will perform complete layout activities from floorplanning to optimization and work closely with circuit designers to optimize noise, parasitics, and yield.

Join a global engineering team with leadership opportunities, driving tape-out readiness and continuous improvement of layout methodologies.

Qualifikationen

• Associate degree + 5+ years designing custom layouts in analog, mixed-signal, RF, or digital domains.
• Bachelor's degree in Electrical/Electronics Engineering (or equivalent) is preferred.
• 5-8 years of experience in High-Speed / Analog / Mixed-Signal layout design in advanced or lower technology nodes.

Aufgaben

• Develop analog, mixed-signal, and high-speed layouts for advanced CMOS technologies.
• Perform floorplanning, placement, routing, matching, shielding, and optimization.
• Debug DRC, LVS, ERC and resolve verification issues.
• Collaborate with circuit designers to optimize layout for noise and yield.
• Lead layout blocks/modules to tape-out readiness.
• Work with global cross-functional teams across geographies.

Kenntnisse

Analog Layout

Layout design

Noise optimization

Parasitics understanding

Debugging

Global collaboration

Lead projects

Communication

Self-motivated

Ausbildung

Associate’s Degree in CS/Math/EE

Bachelor’s degree in Electrical/electronics Eng

Tools

Cadence IC 12.1

LVS

RMAP

SKILL scripting

Perl scripting

Shell scripting

Jobbeschreibung

We are seeking a highly skilled Analog Layout Engineer with strong expertise in advanced CMOS technology nodes to join our VLSI design team. The candidate will be responsible for delivering robust, high‑performance analog, mixed-signal, and high-speed layouts while working closely with design, verification, and global engineering teams. This role demands deep technical expertise, strong ownership, and the ability to execute complex layouts independently.

Key Responsibilities

• Develop high-quality analog, mixed-signal, and high-speed layouts for advanced CMOS technologies.
• Perform complete layout activities including floorplanning, placement, routing, matching, shielding, and optimization.
• Execute and debug DRC, LVS, ERC, and resolve complex physical verification issues.
• Implement advanced layout techniques to meet performance, power, area (PPA), reliability, and manufacturability requirements.
• Address FinFET-specific challenges, including restrictive DRC rules and advanced node limitations.
• Work closely with circuit designers to optimize layout for noise, matching, parasitics, and yield.
• Lead layout blocks or modules independently and drive them to tape‑out readiness.
• Collaborate effectively with global cross‑functional teams across geographies.
• Contribute to continuous improvement of layout methodologies and best practices.
• Hands‑on experience or strong familiarity with GlobalFoundries (GF) process nodes, including FinFET technologies and lower geometry nodes, covering analog/mixed‑signal design challenges, device characterization, and performance optimization.
• Hands‑on experience in Analog / Mixed‑Signal / High‑Speed layout design.
• Strong exposure to advanced technology nodes, including:
• TSMC 2nm, 3nm, 5nm, 7nm, 14nm
• Solid understanding of physical and electrical effects, parasitics, EM/IR, and reliability considerations.
• Sound knowledge and hands‑on experience in FinFET technology, layout design challenges, and DRC constraints.
• Experience working on lower technology nodes with complex layout rules.

Tools & Technical Skills

• Cadence IC 12.1
• Minimum 3+ years of experience using layout design and verification tools such as Cadence, LVS, RMAP, or equivalent.
• Strong debugging and problem‑resolution skills in physical verification.
• Scripting knowledge in SKILL, Perl, and Shell is an added advantage.

Education & Experience Requirements

Candidates should meet one of the following criteria: Associate’s Degree in Computer Science, Mathematics, Electrical Engineering, or related field + 5+ years of experience designing custom layouts in analog, mixed‑signal, RF, or digital domains

Preferred Qualification:

• Bachelor’s degree in Electrical or Electronics Engineering (or equivalent)
• 5 to 8 years of experience in High-Speed / Analog / Mixed‑Signal layout design in advanced or lower technology nodes.
• Strong communication and collaboration skills
• Proven ability to work effectively with global engineering teams
• Excellent analytical and problem‑solving abilities
• Ability to lead projects independently and coordinate with team members
• Self‑motivated, detail‑oriented, and quality focused

Why Join Us

• Opportunity to work on cutting‑edge semiconductor technologies
• Exposure to industry‑leading advanced nodes
• Collaborative and engineering‑driven work culture
• Clear ownership, technical growth, and leadership opportunity.