Senior IP Verification Engineer

SiValley Technologies Pvt Ltd; Bengaluru; On-site; INR 600,000 - 900,000; Full time

Job summary

SiValley Technologies Pvt Ltd in Bengaluru invites an experienced verification engineer to drive IP, subsystem and full‑chip verification using Verilog/SystemVerilog and HVL methodologies.

You will develop verification plans, document test bench architectures, execute tests, close issues with designers and generate test/coverage reports while collaborating with geographically distributed teams.

Qualifications

• Experience in IP/subsystem/chip level verification and end-to-end verification.
• Expertise in Verilog/SystemVerilog and HVL simulations (GLS, PA, AMS).
• Knowledge of UVM/OVM verification methodologies (CDV/MDV).
• Proficient in Perl and Python scripting for test automation.
• Good communication and ability to work with distributed teams.

Responsibilities

• Understand specs and clarify queries with designers/architects.
• Develop verification plans and map them to requirements.
• Document test bench architecture and execution strategies.
• Execute tests and achieve coverage closure.
• Collaborate with designers to close open issues.
• Generate test and coverage reports and prepare weekly status updates.

Skills

Verilog/SystemVerilog

UVM/OVM

C/C++

Perl

Python

Education

B.E./B.Tech in Electrical or Electronics

Tools

SystemVerilog GLS

PA (Power Aware)

AMS

Job description

Job Description:

• Responsible for IP or Subsystem or full-chip level verification.
• For IP verification, responsibility will be end-to-end. Scripting languages Perl, Python.
• Expertise in Verilog and HVL like System VerilogGLS, Power Aware (PA), Analog-Mixed signal (AMS)) simulations.
• Assertions Expertise in verification methodologies like UVM/OVM based CDV (constraint driven verification)/MDV (metric driven verification). Experience working with geographically distributed teams.
• Experience in verification at both module level and chip level Protocols worked on USB, I2S, SPDIF.
• Expertise in programming language C/C++ Good verbal and written communication skills.

Responsibilities will include one or more of the following:

• Understanding spec, interact w/ designers/architect to get queries clarified
• Development of vPlans, ensure complete mapping to requirements
• Document test bench architecture
• Execute tests and coverage closure
• Work w/ designers to close on open issues
• Generate test/coverage reports
• Prepare weekly status report

Education:B.E/B.Tech or M.E/M.Tech/M.S in Electrical or Electronics

SiValley provides services including IP enabled services to Semiconductor, EDA companies in Physical Design, Physical Verification, Analog and Mixed Signal Design, CAD Methodology and Real Time Embedded / Firmware applications development.