FPGA IP Software Development Engineer

Altera; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

Altera is seeking a highly skilled FPGA IP Software Development Engineer in Bengaluru, Karnataka. In this role, you will manage the entire FPGA Soft IP development lifecycle from architecture design to hardware validation.

The ideal candidate will possess over 7 years of experience in RTL Design using System Verilog, Verilog, or VHDL, and must be proficient with major FPGA tools like Altera Quartus and Xilinx Vivado. Candidates with strong collaboration skills and scripting experience will excel in this position.

Qualifications

• 7+ years of experience in production-grade RTL development.
• Strong knowledge of static verification methodologies.
• Experience in embedded SoC architectures preferred.

Responsibilities

• Drive the architecture, development, and implementation of Soft IP solutions.
• Manage the full FPGA tool flow including synthesis and static timing analysis.
• Validate RTL functionality on evaluation boards with lab equipment.

Skills

RTL Design Engineering

System Verilog

Verilog

VHDL

Automation with Tcl

Automation with Python

Automation with Shell scripting

Education

Bachelor’s or master’s degree in Electronics Engineering, Electrical Engineering, VLSI, Embedded Systems

Tools

Altera Quartus Prime

Xilinx Vivado

Microchip Libero

Job description

## FPGA IP Software Development EngineerApplylocations: Bengaluru, Karnataka, Indiatime type: Full timeposted on: Posted Todayjob requisition id: R02686# **Job Details:**### ## **Job Description:**We are seeking a highly skilled and motivated **RTL Design Engineer** to drive the architecture, development, and implementation of our Soft IP solutions. In this role, you will own the end-to-end FPGA Soft IP development lifecycle—from micro-architecture definition and RTL coding to timing closure, simulation, and physical hardware validation. You will work closely with embedded software, hardware, and systems engineering teams to deliver robust, high-performance FPGA Soft IP solution solutions. **Key Responsibilities*** **RTL Architecture & Coding**: Define micro-architecture and implement clean, efficient, and reusable RTL code using **System Verilog**, **Verilog**, or **VHDL**.* **IP Integration & Flow Management**: Drive the full FPGA tool flow including synthesis, place-and-route (P&R), constraints creation, and static timing analysis (STA).* **Timing Closure**: Resolve complex multi-clock designs, Clock Domain Crossing (CDC) anomalies, and timing violations to ensure robust operation.* **Verification & Simulation**: Develop testbenches and run block-level behavioral simulations to thoroughly debug and validate logic functionality before target implementation.* **Hardware Bring-up & Debug**: Validate RTL functionality on actual evaluation boards using lab equipment like logic analyzers, oscilloscopes, and protocol compliance testers.* **Cross-functional Collaboration**: Collaborate with software and board-level hardware teams to establish specifications, interface architectures, and system integration paths.**Required Qualifications & Technical Skills*** **Education**: Bachelor’s or master’s degree in Electronics Engineering, Electrical Engineering, VLSI, Embedded Systems, or a closely related technical discipline.* **Hardware Description**: 7+ years of dedicated experience writing production-grade RTL using **System Verilog, Verilog, or VHDL**.* **Toolchain Expertise**: Hands-on proficiency with major FPGA vendor suites like **Altera Quartus Prime**, AMD / **Xilinx Vivado** or **Microchip Libero**.* **Analysis & Linting**: Strong familiarity with static verification methodologies including Linting, CDC validation, and constraint troubleshooting.* **Scripting Skills**: Ability to automate tool workflows using **Tcl, Python, or Shell scripting**.**Preferred / Bonus Skills*** Familiarity with embedded SoC architectures (e.g., ARM Cortex, RISC-V) and hardware-software co-design. ### ## **Qualifications:**### ## **Job Type:**Regular### ## **Shift:**Shift 1 (India)### ## **Primary Location:**Bengaluru, Karnataka, India### ## **Additional Locations:**### ## **Posting Statement:**All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.