FPGA SW Validation Engineer

844 Altera Semiconductor Technology India Pvt. Ltd.; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

844 Altera Semiconductor Technology India Pvt. Ltd. is looking for an experienced FPGA/ASIC Design Engineer in Bengaluru, Karnataka. The role involves validating compiler optimizations, creating designs with HDLs, and collaborating in cross-functional teams.

Candidates should have a Master’s/Bachelor’s in Electronics and at least 5 years of relevant experience. Good knowledge of FPGA technologies and debugging tools is essential. The position offers a regular job type with shifts.

Qualifications

• 5+ years in FPGA/ASIC design, RTL coding, verification, and hardware debugging.
• Experience with FPGA devices like Agilex and Virtex.

Responsibilities

• Validates and researches compiler optimizations and debugging features.
• Creates designs using HDLs and verifies them.
• Regresses designs during each release for QoR.

Skills

FPGA/Digital Logic Design

RTL design and verification using VHDL/Verilog/SystemVerilog

FPGA Partial Reconfiguration (PR)

Hardware debugging skills using SignalTap/ChipScope

Simulation/verification of digital designs using VCS/Questa/Xcelium

Knowledge of Unix/Linux and scripting

Knowledge of PCIe, Ethernet, Avalon bus protocols

Education

Master’s/Bachelor’s Degree in Electronics/VLSI/Digital Design

Tools

Quartus Design Software

Xilinx Vivado

Synplify

Job description

Responsibilities

• Validates and researches the compiler optimizations, Partial Reconfiguration (PR) flow, debugging features like SignalTap & System Console using Quartus Design Software and Altera FPGA hardware.
• Creates designs using HDLs and Altera IPs and verifies them for functionality and timing on Altera FPGA hardware boards.
• Regresses designs during each release for QoR and monitors performance over targeted FPGA devkits to assess improvements.
• Collaborates with cross‑functional teams to develop and improve validation strategies for compiler/PR validation and help resolve customer issues as they occur.

Qualifications

Education: Master’s/Bachelor’s Degree in Electronics/VLSI/Digital Design or related disciplines.

Experience: 5+ years in FPGA/ASIC design, RTL coding, verification, and hardware debugging.

• FPGA/Digital Logic Design, RTL design and verification using VHDL, Verilog or SystemVerilog.
• Experience with FPGA devices such as Agilex and Virtex and tools like Altera Quartus, Xilinx Vivado, Synplify.
• Good experience in FPGA Partial Reconfiguration (PR) flow and hardware debugging skills using SignalTap or ChipScope.
• Good experience with simulation/verification of digital designs using VCS, Questa, Xcelium, STA and hardware validation of FPGA designs.
• Knowledge of Unix/Linux along with automation scripting using Shell, Perl/TCL or Python.
• Knowledge of PCIe, Ethernet, Avalon bus protocols, AHB, AXI, HPS and high‑speed interfaces.

Job Details

Job Type: Regular
Shift: Shift1 (India)
Primary Location: Bengaluru, Karnataka, India

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.