Senior Engineer - SOC Verification

PeopleStrong; Bengaluru; On-site; INR 1,600,000 - 2,900,000; Full time

Job summary

LTST-L&T Semiconductor Technologies Limited in Bengaluru seeks a Senior Engineer in SoC Design Verification to lead SV/UVM based verification strategies for complex SoCs. You will architect reusable testbenches, drive coverage, and mentor peers to ensure high-quality verification across blocks and chips.

The role requires hands-on SystemVerilog, UVM, coverage-driven verification, SV assertions, and formal methods, with a strong emphasis on full lifecycle verification.

Qualifications

• We are seeking 3+ years of ASIC/SoC verification experience with SV/UVM.
• Strong background in building reusable verification environments and VIP.
• Experience with coverage-driven verification, functional/code coverage, and SV assertions.
• Hands-on full verification lifecycle from test plans to closure.
• Bachelor’s or Master’s in Electronics/EE/CE or related field.
• Knowledge of Formal verification is a plus.

Responsibilities

• Architect and develop reusable testbenches and VIP using SystemVerilog and UVM.
• Drive coverage closure and ensure functional and code coverage across SoC components.
• Implement SV assertions and coverage-driven verification strategies.
• Utilize formal verification to complement simulations.
• Develop test plans and execute at block, subsystem, and full-chip levels.
• Lead debug activities and mentor junior engineers in SV/UVM practices.
• Collaborate with design/architecture teams to define verification strategies.
• Drive continuous improvements in verification methodologies.

Skills

SystemVerilog (SV)

UVM

Coverage-driven verification

SV assertions

Formal verification

Testbench development

Education

Bachelor of Technology (BTech)

Tools

VIP development

Reusable testbenches

Job description

• LTST-L&T Semiconductor Technologies Limited

Posted On 17 Apr 2026

End Date 14 Oct 2026

Required Experience 4 - 7 years

Skills

Knowledge & Posting Location

Bachelor of Technology (BTech)

Job Description

Position Overview:

We are looking for a highly experienced Senior Engineer in SoC Design Verification to join our dynamic team and contribute to the development of cutting-edge SoC solutions.

As a Senior Engineer in SoC Design Verification, you will play a key role in leading the SV/UVM based Subsystem and SoC verification strategy, planning, and execution for complex SoC projects. You will collaborate closely with cross-functional teams to ensure the highest quality and performance standards for our SoC products. This role requires deep technical expertise, leadership skills, and a passion for solving challenging verification problems.

Key Responsibilities:

• Architect and develop reusable testbenches andVerification IP (VIP) usingSystemVerilog andUVM to create scalable verification environments from scratch.
• Drivecoverage closure, ensuring thoroughfunctional coverage andcode coverage across all SoC components.
• Implement and manageSV assertions andcoverage-driven verification strategies to validate designs effectively.
• Utilize formal verification methods and tools to verify complex blocks and subsystems, complementing simulation-based verification.
• Develop comprehensive test plans and ensure their execution at the block, subsystem, and full-chip levels.
• Lead debug activities and identify design and verification bottlenecks early in the development cycle.
• Mentor junior engineers on best practices for SV/UVM, reusable verification, assertions, and coverage analysis.
• Collaborate with design, architecture, and system-level teams to define and implement verification strategies that meet stringent quality and performance goals.
• Drive continuous improvement of verification methodologies and tools to enhance team efficiency and quality.

Requirements:

• 3+ years of experience in ASIC/SoC verification, specializing inSystemVerilog (SV) andUniversal Verification Methodology (UVM).
• Proven expertise in buildingreusable verification environments andVIP development from the ground up.
• Strong experience withcoverage-driven verification, includingfunctional and code coverage analysis and closure.
• Expertise in writing and debuggingSV assertions and applyingformal verification techniques.
• Hands-on experience with the full verification lifecycle, from test plan creation to regression analysis and closure.
• Strong problem-solving, debugging, and analytical skills in a fast-paced environment.
• Bachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or related field.

Nice to Have:

• Experience withPre-Silicon Validation, including test environment setup and validation strategies.
• Proficiency inFPGA prototyping andhardware emulation to complement verification strategies.
• Familiarity withARM-based SoC architectures and high-performance SoC designs for applications such as IP Cameras, automotive, or AI/ML.
• Knowledge of low-power verification andformal verification techniques.

Why Join Us?:

• Be part of a team pushing the boundaries of ASIC SoC design.
• Work on cutting-edge technology in a collaborative and innovative environment.
• Competitive salary and benefits.
• Opportunities for growth and leadership within the company.