Senior Engineer IP Verification - Digital Design Verification

Micron Technology, Inc.; Hyderabad; On-site; INR 1,200,000 - 2,500,000; Full time

Benefits offered by this job

Medical, dental & vision plans

Paid time off

Paid holidays

Job summary

Micron Technology, Inc. is seeking a Senior Engineer IP Verification in Hyderabad to drive RTL verification for DRAM architectures. You will develop SV/UVM testbenches, run constrained-random tests, analyze results, and close coverage gaps before tapeout.

Collaboration with global teams and proactive tooling adoption are expected. You should have a Electronics Engineering degree (B.E./B.Tech or equivalent) with substantial experience in RTL verification, scripting, and memory design

Qualifications

• Bachelor’s degree in Electronics Engineering or related field with 4–6 years of experience or postgraduate degree with 2–4 years of experience.
• Experience building SV/UVM-based verification testbenches at block level.
• Strong scripting skills (Perl, Python) for test generation and automation.
• Hands-on verification of DRAM/memory architectures.
• Familiarity with EDA tools and RTL verification methodologies.

Responsibilities

• Define verification scope, strategy, and plans for block/RTL verification.
• Develop and maintain verification testbenches and test vectors using SV/UVM.
• Run directed and constrained-random tests; triage failures and analyze results.
• Close verification metrics (functional/coverage) and identify holes pre-tapeout.
• Provide verification support across designs; simulate, analyze, and debug block RTL.

Skills

RTL verification

SV/UVM

Scripting (Perl/Python)

Debugging

Team collaboration

Education

Bachelor’s degree in Electronics Engineering

Postgraduate degree in Electronics Engineering

Tools

Virtuoso

Xcelium

SimVision

Verdi

Verisium

Job description

Req. ID: JR110953 Senior Engineer IP Verification - Digital Design Verification

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Responsibilities will include, but are not limited to:

• Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification
• Develop, execute, and maintain verification testbenches and test vectors using digital simulation tools and methodologies (SV-UVM)
• Run directed and constrained-random tests and regressions; analyze results and triage failures.
• Close verification metrics (functional coverage / code coverage as applicable) and identify verification holes to demonstrate readiness toward tapeout
• Provide verification support to design projects by simulating, analyzing, and debugging block level RTL. Develop Test cases/Stimulus to increase the functional coverage for all DRAM architectures and features.
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.
• Debug RTL / testbench / environment issues and partner with design engineers to identify root cause, propose fixes, and prevent recurrence.
• Provide verification status and summaries to stakeholders; communicate risk clearly and drive action closure.
• Good understanding of digital circuits and experience in RTL Verification. Understand the usage of tools like Virtuoso, Xcellium, Simvision, Verdi/Verisium.
• Hands on experience in building SV, UVM based Verification testbenches at Block Level.
• Good scripting skills using perl, python
• Previous work experience in DRAM memory related fields and Must possess good communication, debugging skills and ability to work well in a team.
• Should be proactive in exploring and leveraging AI-related tools in day-to-day tasks.
• Proactively adopt approved AI tools to support verification workflows, scripting, and methodology improvements, maintaining full responsibility for technical decisions.

Bachelor’s with 4-6 years of experience or Post Graduate Degree in Electronics Engineering or related engineering field required with 2-4 years of experience.

Job Profile(s):

Semiconductor Design Engineer 3

Relocation level: (TBD)

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.