Staff Engineer IP Verification - Digital Design Verification

Micron Technology, Inc.; Hyderabad; On-site; INR 6,000,000 - 8,000,000; Full time

Job summary

Micron Technology, Inc. in Hyderabad seeks a Staff Engineer for IP Verification in Digital Design Ver\ification. You will own end-to-end verification of complex DRAM memory IPs, lead verification efforts, and drive quality across projects.

You will develop SV/UVM testbenches, run regression tests, and mentor junior engineers while coordinating with global teams to enable on-time tapeout. Strong RTL knowledge and scripting skills are essential; experience with Virtuoso, Xcelium, SimVision, and

Qualifications

• Bachelor's or higher in electronics engineering or related field.
• 7+ years in verification of DRAM/memory or RTL-level designs.
• Proven ability to lead and mentor technical teams.

Responsibilities

• Understand design specs and define verification scope for RTL blocks.
• Develop, execute, and maintain SV/UVM testbenches and vectors.
• Run directed and constrained tests; triage failures and improve coverage.
• Collaborate with distributed teams to drive verification methodology.
• Provide status updates and risk assessments to stakeholders.

Skills

SV/UVM

Testbench development

RTL verification

Digital design

Python

Perl scripting

Debugging

Team leadership

Mentoring

Education

Bachelor's degree in Electronics Engineering

Postgraduate degree in Electronics Engineering

Tools

Virtuoso

Xcelium

SimVision

Verdi/Verisium

Job description

Req. ID:
JR110929 Staff Engineer IP Verification - Digital Design Verification

Our vision is to transform how the world uses information to enrich life for all.

Micron Technology is a world leader in innovating memory and storage solutions that accelerate the transformation of information into intelligence, inspiring the world to learn, communicate and advance faster than ever.

Complete ownership of verification and end to end analysis of complex block level custom designs with advanced low power and power management technologies spread across multiple categories such as DDR5, LPDDR5, DDR6 and LPDDR6 that are capable of operating at high speeds of up to 11,4000MT/s.

Staff-Level Expectations:

• Lead verification efforts for strategic IPs and complex subsystems.
• Influence verification methodology across projects.
• Mentor junior engineers and drive verification quality, productivity, and innovation.
• Provide technical leadership across geographically distributed teams.
• Ability to lead team, guide and set the direction for the verification effort for any project that the team undertakes.
• Define roadmap and future scope of verification methodologies.

Roles and Responsibilities:

• Understand design specifications and define verification scope, strategy, and plans for block/chip RTL verification
• Develop, execute, and maintain verification testbenches and test vectors using digital simulation tools and methodologies (SV-UVM)
• Run directed and constrained-random tests and regressions; analyze results and triage failures.
• Close verification metrics (functional coverage / code coverage as applicable) and identify verification holes to demonstrate readiness toward tapeout
• Provide verification support to design projects by simulating, analyzing, and debugging block level RTL. Develop Test cases/Stimulus to increase the functional coverage for all DRAM architectures and features.
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements. Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.
• Debug RTL / testbench / environment issues and partner with design engineers to identify root cause, propose fixes, and prevent recurrence.
• Provide verification status and summaries to stakeholders; communicate risk clearly and drive action closure.
• Good understanding of digital circuits and experience in RTL Verification. Understand the usage of tools like Virtuoso, Xcellium, Simvision, Verdi/Verisium.
• Hands on experience in building SV, UVM based Verification testbenches at Block Level.
• Good scripting skills using perl, python
• Previous work experience in DRAM memory related fields and Must possess good communication, debugging skills and ability to work well in a team.
• Should be proactive in exploring and leveraging AI-related tools in day-to-day tasks.
• Proactively adopt approved AI tools to support verification workflows, scripting, and methodology improvements, maintaining full responsibility for technical decisions.

Bachelor’s with 7-9 years of experience or Post Graduate Degree in Electronics Engineering or related engineering field required with 6 - 8 years of experience.

Job Profile(s):

• Semiconductor Design Engineer 4
• Relocation level: (TBD)

Before Getting Started

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• If you are selected to interview for a position, you must notify your direct supervisor before participating in the interview process.

As a world leader in the semiconductor industry, Micron is dedicated to your personal wellbeing and professional growth. Micron benefits are designed to help you stay well, provide peace of mind and help you prepare for the future. We offer a choice of medical, dental and vision plans in all locations enabling team members to select the plans that best meet their family healthcare needs and budget. Micron also provides benefit programs that help protect your income if you are unable to work due to illness or injury, and paid family leave. Additionally, Micron benefits include a robust paid time-off program and paid holidays. For additional information regarding the Benefit programs available, please see the Benefits Guide posted on Benefits | Micron Technology, Inc

Micron is proud to be an equal opportunity workplace and is an affirmative action employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, age, national origin, disability, protected veteran status, gender identity or any other factor protected by applicable federal, state, or local laws.