Senior Engineer II - Verification

Microchip Technology Inc.; Chennai District; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

Microchip Technology Inc. is seeking a Senior Verification Engineer for its Secure Computing Products Group in Chennai, India. The role involves the verification of complex blocks within ARM-based SoCs and requires strong expertise in System Verilog, UVM methodology, and collaboration with multiple teams.

The ideal candidate will have a Bachelor’s degree with significant experience in ASIC verification and will provide technical guidance to junior engineers while improving verification methodologies.

Qualifications

• 7–9 years of experience in ASIC/SoC functional verification.
• Strong expertise in System Verilog and UVM methodology.
• Hands-on experience developing verification environments.

Responsibilities

• Own the verification of complex blocks and subsystems.
• Define test plans and drive coverage closure.
• Develop test environments using System Verilog and UVM.

Skills

System Verilog

UVM methodology

Python

C++

Digital design fundamentals

Debugging skills

Education

Bachelor’s degree in Electrical/Electronic Engineering

Tools

Cadence

Synopsys

Mentor verification platforms

Job description

Job Description

As a Senior Verification Engineer in the Secure Computing Products (SCG) Group at Microchip, the individual will be part of a larger digital logic design effort responsible for designing state‑of‑the‑art hardware embedded controller solutions. This position requires someone comfortable with all aspects of digital design development and able to adapt to constantly evolving requirements. The role demands strong communication and organizational skills and collaboration with multiple functional groups to create integrated solutions that meet embedded controller needs of various industries.

Job Responsibilities

• Own the verification of complex blocks and subsystems within ARM‑based SoCs.
• Perform digital design verification at the block level and chip‑level functional verification.
• Define test plans from design specifications, implement constrained‑random and directed tests, and drive coverage closure.
• Develop test environments using System Verilog and UVM verification methodologies.
• Integrate with RTL and conduct basic simulation bring‑up for the design.
• Create multiple test cases as per the test plan and launch regressions.
• Generate code/functional coverage, analyze coverage results, and correlate with the test plan.
• Debug RTL and testbench issues, perform root‑cause analysis, and collaborate with design teams to resolve bugs.
• Contribute to AI/automation initiatives for regression management, coverage tracking, and debug automation.
• Work with architects and validation engineers to ensure end‑to‑end feature completeness and quality.
• Provide technical guidance and mentorship to junior engineers as required.
• Continuously improve verification methodology, reuse, and efficiency.

Requirements / Qualifications

• Bachelor’s degree with 7–9 years of experience in ASIC/SoC functional verification, or Master’s degree with 6–8 years in Electrical/Electronic Engineering or related field.
• Strong expertise in System Verilog and UVM methodology.
• Hands‑on experience developing block/subsystem/SoC‑level verification environments.
• Solid understanding of AMBA, USB, I2C, SPI and eSPI protocols.
• Good understanding of digital design, RTL fundamentals, and simulation/debug flows.
• Familiarity with scripting (Python/TCL/Perl) for automation.
• Good programming skills with languages such as C, C++.
• Experience working with Cadence, Synopsys, or Mentor verification platforms is an asset.
• Exposure to AI/ML‑based verification, emulation, or acceleration is a plus.
• Excellent communication, teamwork, problem‑solving abilities, strong analytical and debugging skills.
• Highly motivated, detail‑oriented, and committed to delivering quality results.
• Ability to lead cross‑site teams and manage complex design programs.

Travel Time

0% – 25%