Senior Engineer HDD

Fortune Consultancy; Chennai District; On-site; INR 1,500,000 - 2,300,000; Full time

Job summary

Fortune Consultancy in Chennai, India, is seeking an experienced FPGA engineer to drive RTL design using VHDL and oversee synthesis, timing analysis, and design constraints for high-speed avionics interfaces.

The role requires strong knowledge of DO-254 lifecycle, exposure to Xilinx/Altera architectures, and hands-on work with PCIe, Ethernet, DDR, JESD and SERDES. You will also enhance test benches and verification environments.

Qualifications

• Experience in RTL design and RTL verification using VHDL/Verilog.
• Familiarity with DO-254 lifecycle and high-speed interfaces.
• Exposure to FPGA architectures and timing closure challenges.

Responsibilities

• Requirements generation and RTL design using VHDL.
• Understand DO-254 lifecycle.
• FPGA design, synthesis, timing analysis and design constraints.
• Exposure to Xilinx/Altera FPGA architectures.
• Experience with PCIe, ARINC, Ethernet, DDR, JESD, SERDES.
• Improve test benches, simulation and verification environments.

Skills

Verilog/VHDL

Vivado/Quartus

Static Timing Analysis

Digital design

Radar DSP

High-speed protocols

Timing closure

Tcl scripting

Logic analyzers

Tools

Vivado

Quartus

PCIe

DDR

JESD

SERDES

Ethernet

Job description

Role & responsibilities

• Requirements generation and RTL design using VHDL
• Strong understanding of the DO-254 development lifecycle
• FPGA design, synthesis, timing analysis, and design constraints
• Exposure to Xilinx/Altera FPGA architectures
• Experience with PCIe, ARINC, Ethernet, DDR, JESD, and SERDES interfaces
• Continuously improve test benches, simulation, and verification environments

Required Skills

• Proficiency in Verilog/VHDL
• Hands-on experience with Vivado or Quartus
• Expertise in Static Timing Analysis (STA), floorplanning, and timing closure
• Strong digital design and analytical skills
• Knowledge of Signal Processing and Radar Digital Signal Processing
• Experience balancing Area, Power, and Speed trade-offs
• System-level debugging using Tcl scripting and logic analyzers

Preferred candidate profile

Requirements Generation, RTL design using VHDL, Good knowledge in DO-254 lifecycle. Good exposure to synthesis, timing analysis and design constraints, FPGA architecture: Vilinx/Altera, Exposure to PCIe, Arinc protocols etc., Continuously improve test and simulation environment. Position Specific Requirements Proficiency in Verilog/VHDL, experience with Vivado or Quartus, and expertise in timing closure and high-speed protocols. Good in Digital and analytical skill. Good in Signal processing Position Specific Skills Proficiency in PCIe/Ethernet protocols and Multi-Gigabit Transceivers (SERDES). Worked in the areas like High speed interface like PCIe, DDR, JESD & Ethernet. Expertise in Static Timing Analysis (STA), floorplanning, and timing closure. Balancing architectural trade-offs between Area, Power, and Speed performance. System-level troubleshooting using Tcl scripting and logic analyzers. Expertise in RADAR Digital Signal Processing.