Senior Engineer, CAD

1840 Micron Tech. OP India LLP; Hyderabad; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

1840 Micron Tech. OP India LLP is looking for a CAD Engineer in Hyderabad to enhance productivity in electronic design automation. You will collaborate with layout teams to develop innovative solutions and improve designs using AI methodologies.

The ideal candidate has over 5 years of experience, a degree in Engineering, and proficiency with tools like Cadence and Synopsys. Strong programming skills in languages like Python and Perl are essential.

Qualifications

• 5+ years of experience in layout automation, physical verification, or related domains.
• Hands-on experience with industry standard tools for memory layouts.
• Strong programming fundamentals and proficiency in Linux.

Responsibilities

• Work closely with memory layout teams to solve daily challenges.
• Proactively identify problem areas for improvement and propose solutions.
• Develop AI-driven methodologies for semi-automated floorplanning.

Skills

Layout automation

Physical Verification

Programming in Skill, Perl, Python, and Tcl

Custom memory layouts

Problem-solving

Education

Bachelor’s or Master’s in Electronics, Electrical, or Computer Engineering

Tools

Cadence Virtuoso

Synopsys Custom Compiler

Pulsic Unity

Totem/VoltusXFA/XA

Linux OS

Job description

Job Description

As a CAD Engineer at Micron Technology, Inc., you will work in a collaborative production support role evaluating, improving EDA and debugging both in‑house and commercial Electronic Design Automation (EDA) tools and flows for the physical layout, verification and design of CMOS integrated circuits. You will partner closely with layout design teams to increase their productivity and work efficiency.

Responsibilities

• Work closely with memory layout teams to solve daily challenges and provide complete solutions.
• Proactively identify problem areas for improvement, propose, and develop innovative solutions.
• Develop methodologies for highly reliable layout with faster time‑to‑market approaches.
• Lead layout flows implementation using AI‑assisted and automated workflows, including copilot‑based assistants, agentic AI flows, and rule‑aware automation to accelerate placement, routing, and optimization.
• Continuously evaluate and implement new tools and technologies to improve current layout development flows.
• Provide guidance and mentorship to junior team members.
• Develop and deploy AI‑enabled methodologies for semi‑automated floorplanning and parasitic estimation.

Qualifications

• 5+ years of experience in Layout automation, Physical Verification, or related domains.
• Experience customizing a design environment, automation methodologies, and utilities to increase memory layout productivity.
• Hands‑on experience in place‑and‑router flows for custom memory layouts with industry standard tools such as Cadence Virtuoso, Synopsys Custom Compiler, Pulsic Unity, and Itools.
• Experience with PDN analysis tools such as Totem/VoltusXFA/XA is preferred.
• Experience with Physical Verification flows and analyzing/debugging DRC, ERC, LVS, DFM, and antenna/calibre rule deck issues.
• Good understanding of advanced CMOS process manufacturing and layout design rules, including EMIR, RC‑Extraction, ESD, and latch‑up.
• Strong programming fundamentals and exposure to languages such as Skill (Cadence), Perl, Python, and Tcl.
• Proficiency in Linux operating system.
• Excellent problem‑solving skills with attention to detail and ability to work in a dynamic environment.
• Proven expertise in defining, developing, and scaling AI‑driven automation for complex layout workflows.
• Effective collaboration with global teams and stakeholders.

Education

A bachelor’s or master’s degree in Electronics, Electrical or Computer Engineering.

EEO Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, veteran or disability status.