Senior Engineer - ASIC Design

MosChip; Bengaluru; On-site; INR 1,000,000 - 1,500,000; Full time

Job summary

MosChip is seeking a highly skilled engineer with strong background in logic design, RTL coding, and SoC integration. Candidates should be proficient in Verilog/SystemVerilog and familiar with multi-clock designs and asynchronous interfaces. Knowledge of Lint, CDC, synthesis concepts, ECO fixes, and formal verification is preferred.

Excellent communication and collaborative skills are a must. Join MosChip in advancing semiconductor and embedded system design, with opportunities across Aerospace,

Qualifications

• Experience in logic design and RTL coding is essential.
• Experience in SoC design and integration for complex SoCs is essential.
• Proficiency in Verilog/SystemVerilog is essential.
• Experience in multi-clock designs and asynchronous interfaces is required.
• Experience using ASIC development tools such as Lint and CDC.
• Synthesis and timing concepts knowledge is a plus.
• ECO fixes and formal verification experience.
• Knowledge of AMBA protocols - AXI, AHB, APB, and SoC clocking/reset architecture.
• Excellent oral and written communication skills.
• Proactive, creative, curious, and collaborative.

Skills

Logic design

RTL coding

SoC design

Verilog

SystemVerilog

Multi-clock design

Asynchronous interface

Lint/CDC

Synthesis & timing

ECO fixes

Formal verification

AMBA AXI/AHB/APB

Clocking/reset architecture

Communication skills

Job description

company Overview

MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.

Required Skills

• Experience in Logic design / RTL coding is a must.
• Experience is SoC design and integration for complex SoCs is a must.
• Experience in Verilog/System-Verilog is a must.
• Experience in Multi Clock designs, Asynchronous interface is a must.
• Experience in using the tools in ASIC development such as Lint and CDC.
• Experience in Synthesis / Understanding of timing concepts is a plus.
• Experience in ECO fixes and formal verification.
• Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
• Excellent oral and written communications skills.
• Proactive, creative, curious, motivated to learn and contribute with good collaboration skills