ASIC RTL Design Engineer

MosChip; Hyderabad; On-site; INR 1,500,000 - 2,700,000; Full time

Job summary

MosChip is seeking an experienced RTL/SoC design engineer to contribute to complex ASIC/SoC integration projects. The role demands hands-on Verilog/SystemVerilog expertise, multi-clock domain handling, and familiarity with Lint, CDC, synthesis concepts, and formal verification.

Proactive collaboration and strong communication are essential for cross-functional work. The candidate should be comfortable with AMBA AXI/AHB/APB protocols and robust clocking/reset architectures, and eager to learn in

Qualifications

• Experience in Logic design / RTL coding is a must.
• Experience is SoC design and integration for complex SoCs is a must.
• Experience in Verilog/System-Verilog is a must.
• Experience in Multi Clock designs, Asynchronous interface is a must.
• Experience in using the tools in ASIC development such as Lint and CDC.
• Experience in Synthesis / Understanding of timing concepts is a plus.
• Experience in ECO fixes and formal verification.
• Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
• Excellent oral and written communications skills.
• Proactive, creative, curious, motivated to learn and contribute with good collaboration skills

Skills

RTL coding

SoC design

Verilog

SystemVerilog

Multi-clock designs

Asynchronous interface

Lint

CDC

Synthesis

Timing concepts

ECO fixes

Formal verification

AMBA AXI

AMBA AHB

AMBA APB

Clocking & reset

Communication skills

Collaboration

Job description

company Overview

MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.

Required Skills

• Experience in Logic design / RTL coding is a must.
• Experience is SoC design and integration for complex SoCs is a must.
• Experience in Verilog/System-Verilog is a must.
• Experience in Multi Clock designs, Asynchronous interface is a must.
• Experience in using the tools in ASIC development such as Lint and CDC.
• Experience in Synthesis / Understanding of timing concepts is a plus.
• Experience in ECO fixes and formal verification.
• Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
• Excellent oral and written communications skills.
• Proactive, creative, curious, motivated to learn and contribute with good collaboration skills