Lead Engineer - ASIC Design

MosChip; Bengaluru; On-site; INR 1,200,000 - 2,100,000; Full time

Job summary

MosChip in Bengaluru is seeking an experienced ASIC/SoC design engineer to work on complex SoCs and RTL development. The role emphasizes logic design, verification, and integration across multi-clock systems.

Candidates should have hands-on experience with Verilog/SystemVerilog, AMBA protocols, and ASIC timing concepts. Excellent communication and collaborative skills are essential for cross-functional teamwork and delivering robust silicon designs.

Qualifications

• Experience in Logic design / RTL coding.
• Experience in SoC design and integration for complex SoCs.
• Experience in Verilog/System-Verilog.
• Experience in Multi Clock designs, Asynchronous interface.
• Experience in using the tools in ASIC development such as Lint and CDC.
• Experience in Synthesis / Understanding of timing concepts.
• Experience in ECO fixes and formal verification.
• Knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
• Excellent oral and written communications skills.
• Proactive, creative, curious, motivated to learn and contribute with good collaboration skills.

Skills

Logic design/RTL coding

SoC design & integration

Verilog/SystemVerilog

Multi-clock designs/async interfaces

ASIC tools (Lint, CDC)

Synthesis & timing concepts

ECO fixes & formal verification

AMBA protocols (AXI/AHB/APB)

Communication skills

Collaborative mindset

Job description

company Overview

MosChip is a semiconductor and embedded system design company with a focus on Embedded, Turnkey ASICs, Mixed Signal IP, Semiconductor & Product Engineering and IoT solutions catering to Aerospace & Defense, Consumer Electronics, Automotive, Medical and Networking & Telecommunications.

Required Skills

• Experience in Logic design / RTL coding is a must.
• Experience is SoC design and integration for complex SoCs is a must.
• Experience in Verilog/System-Verilog is a must.
• Experience in Multi Clock designs, Asynchronous interface is a must.
• Experience in using the tools in ASIC development such as Lint and CDC.
• Experience in Synthesis / Understanding of timing concepts is a plus.
• Experience in ECO fixes and formal verification.
• Should have knowledge of AMBA protocols - AXI, AHB, APB, SoC clocking/reset architecture.
• Excellent oral and written communications skills.
• Proactive, creative, curious, motivated to learn and contribute with good collaboration skills