Senior Design Verification Engineer

Acesoft Labs; Hyderabad; Hybrid; INR 1,000,000 - 1,500,000; Full time

Benefits offered by this job

Flexible Working Hours

Transport facility

Competitive Salary

Job summary

Acesoft Labs in Hyderabad, India is seeking a qualified verification engineer to perform pre-silicon full-chip simulations, analyze results, and develop test stimulus to boost memory coverage.

You will work with SystemVerilog, UVM test benches, SPICE/Verilog simulations, and collaborate with the hardware and software teams to ensure functional accuracy in DRAM/SRAM designs. The role requires leadership, strong communication, and the ability to guide junior engineers in a fast-paced environment.

Qualifications

• Strong communication and leadership to guide new team members.
• Analytical expertise in CMOS/gate-level designs.
• Experience with SPICE and Verilog simulations.

Responsibilities

• Pre-Silicon Support: Simulate, analyze, and debug pre-silicon full-chip designs to ensure functional accuracy.
• Test Case Development: Develop stimulus and test cases to increase functional coverage for DRAM, SRAM, and other memory technologies.

Skills

Strong communication

Leadership

Analytical expertise

Team collaboration

Tools

Verilog

SPICE

UVM

Job description

Role & responsibilities

• Pre-Silicon Support: Simulate, analyze, and debug pre-silicon full-chip designs to ensure functional accuracy.
• Test Case Development: Develop stimulus and test cases to increase the functional coverage for DRAM, SRAM, and other emerging memory technologies.

Core Requirements

• Strong Communication Skills: Ability to collaborate effectively within a team.
• Leadership: Guide new team members and engineers, sharing your knowledge and experience.
• Analytical Expertise: Deep understanding of complex CMOS and/or gate-level circuit designs.
• Proficiency in SPICE and/or Verilog simulations.

Preferred candidate profile

Required Skills

• Experience with SystemVerilog, PLI coding, and UVM Test Benches.
• Expertise in DRAM, SRAM, or other memory-related fields.
• Familiarity with AMS verification and co-simulation is a plus.
• Experience with Ethernet, SATA, Perl Scripts, and Debugging is helpful.
• Knowledge of full-chip DDR, gate-level simulation, and SPICE simulation is optional but advantageous.

Perks and benefits

Flexible Working Hours , Transport facility, Competitive Salary