Design and Verification Engineer

Acesoft Labs; Hyderabad; Hybrid; INR 900,000 - 1,350,000; Full time

Job summary

Acesoft Labs in Hyderabad, India, seeks an experienced Verification Engineer to provide verification support for pre-silicon full chip designs, focusing on DRAM and emerging memory architectures. You will develop test benches, create stimuli to improve functional coverage, run regressions, and collaborate with international teams to advance verification methodologies and co-simulation flows.

Ideal candidates have 7+ years in CMOS/Gate-level design, SystemVerilog, UVM, and memory verification,

Qualifications

• 7+ years of experience in memory verification or related field.
• Strong understanding of CMOS and gate-level designs.
• Experience with SystemVerilog, UVM, and PLI.
• Familiarity with SPICE and Verilog simulations.
• Good communication and teamwork skills.

Responsibilities

• Provide verification support by simulating, analyzing and debugging pre-silicon full chip designs.
• Develop test cases and stimuli to increase functional coverage for DRAM and emerging memory architectures and features.
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.
• Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.
• Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.

Skills

CMOS & gate-level design

SPICE familiarity

Verilog simulations

SystemVerilog

PLI coding

UVM test bench

Communication skills

Tools

Verilog simulators

Job description

Role & responsibilities

• Provide verification support to design projects by simulating, analyzing and debugging pre-silicon full chip designs.
• Develop Test cases/Stimulus to increase the functional coverage for all DRAM and emerging memory architectures and features.
• Develop and maintain test benches and test vectors using simulation tools and run regressions for coverage analysis and improvements.
• Co-work with international colleagues on developing new verification flows to take on the challenges in DRAM and emerging memory design.
• Participate in developing verification methodology and verification environments for advanced DRAM and emerging memory products.

Preferred candidate profile

• Basic understanding of CMOS and gate level circuit designs
• Familiarity with SPICE
• Familiarity with Verilog simulations
• Good communication skills and ability to work well in a team

Preferred Qualities

• Analytical capability for complex gate level circuit designs
• Experience in SystemVerilog, PLI coding
• Experience in UVM Test Bench
• Experience in DRAM, SRAM or other memory related fields
• Experience in AMS verification and co-sim
• Experience Level 7+ years