Senior Design Verification Engineer

Sasken Technologies Limited; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Benefits offered by this job

Opportunity to work on cutting-edge verification projects

Collaborative environment

Growth opportunities in advanced verification methodologies

Job summary

A technology solutions company is looking for an experienced Digital Verification Engineer to drive verification activities independently. The ideal candidate should have 8–10 years of hands-on experience in digital verification, with strong knowledge of UVM methodology and System Verilog. Role involves developing verification environments, mentoring junior engineers, and working in a collaborative, fast-paced setting, providing growth opportunities in advanced verification methodologies.

Qualifications

• 8–10 years of hands-on digital verification experience required.
• Strong knowledge of UVM methodology and System Verilog is essential.
• Experience in RFID chip verification is a strong advantage.

Responsibilities

• Develop and update custom UVM verification environments.
• Maintain and enhance existing UVCs through bug fixes.
• Collaborate with cross-functional teams to ensure verification completeness.

Skills

UVM methodology

System Verilog

Debugging skills

Problem-solving skills

Mentoring

Job description

Preferred Location: Bangalore / Ahmedabad

Role Overview

We are seeking an experienced Digital Verification Engineer who can work independently and drive verification activities across multiple digital functional domains. The ideal candidate will have strong expertise in UVM-based verification methodologies and hands‑on execution skills, with the ability to mentor junior engineers when required.

Key Responsibilities

• Develop and update custom UVM verification environments including models, predictors, and specialized components.
• Maintain and enhance existing UVCs through bug fixes and extensions.
• Create and update tests/sequences to improve coverage and verification efficiency.
• Define functional coverage and ensure alignment with the verification plan.
• Debug regressions, including gate-level simulations.
• Provide support and guidance to junior engineers on verification methodology.
• Create and debug digital models of analog blocks.
• Collaborate with cross‑functional teams to ensure verification completeness.

Desired Skills & Experience

• 8–10 years of hands‑on digital verification experience.
• Strong knowledge of UVM methodology and System Verilog.
• Proven ability to work with minimal supervision and deliver results.
• Experience in RFID chip verification or RF system verification is a strong advantage.
• Excellent debugging and problem‑solving skills.
• Ability to mentor and guide junior engineers (while maintaining focus on execution).

Good To Have

• Scripting Knowledge
• Experience Working in Fast‑Paced, Customer‑Facing projects

What We Offer

• Opportunity to work on cutting‑edge verification projects.
• Collaborative environment with scope for both hands‑on execution and technical leadership.
• Growth opportunities in advanced verification methodologies and RF‑related domains.