Principal Engineer

ACL Digital

Bengaluru

On-site

INR 1,500,000 - 2,500,000

Full time

14 days+

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Job summary

A leading engineering firm in Bengaluru is hiring a Senior Design Verification Engineer with 8–14 years of experience to lead verification projects. Responsibilities include developing test plans and collaborating cross-functionally. Candidates should have expertise in SystemVerilog and UVM. This full-time position offers a competitive salary and the chance to work on cutting-edge projects in semiconductor manufacturing.

Qualifications

8–14 years of hands-on experience in ASIC/SoC verification.
Experience in developing and maintaining testbenches from scratch.
Familiarity with version control and CI/CD systems.

Responsibilities

Lead and contribute to the verification of complex IP blocks or SoC subsystems.
Develop test plans, verification strategies, and coverage metrics based on design specifications.
Provide technical guidance and mentorship to junior team members.

Skills

SystemVerilog

UVM

RTL simulation tools (e.g., VCS, Questa)

Scripting languages (Python, Perl, TCL)

Debugging skills

Education

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering

Tools

Verdi

DVE

Job description

Direct message the job poster from ACL Digital

Hiring Expertise/ Leaders for VLSI/ Semiconductors!

Technical Specialist - Design Verification

Experience: 8–14 Years.

About the Role:

We are looking for an experienced and passionate Senior Design Verification Engineer to join our team in Bangalore. The ideal candidate will have a strong background in pre-silicon verification of complex IPs or SoCs and be capable of leading verification efforts across multiple projects.

Key Responsibilities:

Lead and contribute to the verification of complex IP blocks or SoC subsystems.
Develop test plans, verification strategies, and coverage metrics based on design specifications.
Build and maintain constrained-random and directed testbenches using SystemVerilog/UVM.
Collaborate with architects, designers, and other verification engineers to identify and debug design issues.
Develop and maintain verification infrastructure, scripts, and regression systems.
Perform functional and code coverage analysis, driving closure.
Provide technical guidance and mentorship to junior team members.
Participate in silicon bring-up and post-silicon validation when needed.

Required Skills and Qualifications:

B.E./B.Tech or M.E./M.Tech in Electronics, Electrical, or Computer Engineering.
8–14 years of hands-on experience in ASIC/SoC verification.
Strong expertise in SystemVerilog, UVM, and RTL simulation tools (e.g., VCS, Questa).
Solid understanding of verification methodologies, functional coverage, and assertion-based verification.
Experience in developing and maintaining testbenches from scratch.
Strong debugging skills and familiarity with waveform viewers like Verdi or DVE.
Good knowledge of scripting languages (Python, Perl, or TCL) for automation.
Familiarity with version control and CI/CD systems.

Preferred Qualifications:

Experience in formal verification or emulation is a plus.
Familiarity with industry-standard protocols like PCIe, USB, DDR, AMBA (AXI/AHB/APB).
Prior experience in leading a verification team or acting as a verification lead.
Exposure to post-silicon bring-up and validation.

About Company:

ACL Digital, a leader in digital engineering and transformation, is part of the ALTEN Group. At ACL Digital, we empower organizations to thrive in an AI-first world. Our expertise spans the entire technology stack, seamlessly integrating AI and data-driven solutions from Chip to cloud. By choosing ACL Digital, you gain a strategic advantage in navigating the complexities of digital transformation. Let us be your trusted partner in shaping the future.

Seniority level