PCIe Protocol Verification Engineer

Acldigital; Hyderabad; Hybrid; INR 167,400 - 223,200; Full time

Job summary

A digital innovation company in Hyderabad seeks a PCIe Protocol Verification Engineer with over 5 years of experience. The candidate will perform compliance verification of PCIe-based SystemC IPs, integrate various components for protocol-level verification, and analyze specifications. A deep understanding of the PCIe protocol and strong debugging skills are essential. The job offers flexibility in location – either onsite in Hyderabad or remote working arrangements.

Qualifications

• 5+ years of experience in PCIe protocol verification.
• Strong debugging and problem-solving skills.
• Good understanding of regression setup and scripting.

Responsibilities

• Perform functional and compliance verification of PCIe-based SystemC IPs.
• Integrate SystemC PCIe IPs for protocol-level verification.
• Work closely with design, architecture, and validation teams.

Skills

Hands-on experience with Avery PCIe VIP

Knowledge of PCIe protocol (Gen5/Gen6 or higher)

Experience in SystemVerilog / UVM methodology

Debugging skills using simulators like Questa, VCS, or Xcelium

Familiarity with coverage-driven verification

Understanding of verification flow and scripting

Excellent communication skills

Education

B.E/M.E/M.Tech or B.S/M.S in EE/CE

Job description

ACL Digital is a design‑led Digital Experience, Product Innovation, Solutions, and Consulting offerings leader. From strategy, to design, implementation, and management we help accelerate innovation and transform businesses. Keeping customer journeys and design at the core, it is committed to enable large Enterprises, SMBs and start‑ups to transform. A pioneer in delivering Business Innovation, Integration and Transformation through disruptive technologies, ACL Digital brings in competitive advantage, innovation, and fresh perspectives to business challenges. With a multi‑cultural and transnational talent and as part of the ALTEN Group comprising over 37,000 employees spread across more than 25 countries, it promotes a collaborative knowledge‑building environment.

About Company

Roles and Responsibility

Job Title: PCIe Protocol Verification Engineer

Job Description

• Perform functional and compliance verification of PCIe‑based SystemC IPs and subsystems.
• Integrate SystemC PCIe IP/Subsystem in Avery PCIe VIPs and utilize for protocol‑level verification.
• Debug complex issues across transaction, data link, and physical layers of PCIe.
• Analyze and interpret PCIe specifications for test planning and coverage.
• Work closely with design, architecture, and validation teams to ensure feature completeness and spec compliance.
• Generate and review verification plans, test reports, and coverage metrics.

Required Skills

• Strong hands‑on experience with Avery PCIe VIP (integration, debug, customization).
• In‑depth knowledge of PCIe protocol (Gen5/Gen6 or higher).
• Solid experience in SystemVerilog / UVM methodology.
• Strong debug and problem‑solving skills using simulators like Questa, VCS, or Xcelium.
• Familiarity with coverage‑driven verification and constraint random testing.
• Good understanding of verification flow, regression setup, and scripting (Python/Perl/Shell).
• Excellent communication skills and ability to work independently in a fast‑paced environment.

Qualification : B.E/M.E/M.Tech or B.S/M.S in EE/CE

Experience Level : 5 years+

Location : To be placed on Xilinx Hyderabad location or can work remotely : AMD, Hyderabad

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