Senior Design Automation Engineer

Tsavorite Scalable Intelligence; Bengaluru; On-site; INR 2,000,000 - 3,200,000; Full time

Job summary

Tsavorite Scalable Intelligence seeks a CAD Hardware Engineer with strong RTL design and Design Verification to own verification infrastructure across RTL, DV, and firmware. You will partner with EDA vendors to improve tool performance and support large-scale chiplet flows.

The role involves coordinating with India and USA teams, maintaining build systems, and driving regression automation in a fast-paced startup environment.

Qualifications

• Bachelor's or Master's degree in Electrical or Computer Engineering with 5+ years in VLSI design or DV.
• Strong RTL design and/or Design Verification experience.
• Hands-on with simulation and emulation tool flows.
• Git, release management, and CI/CD experience.

Responsibilities

• Own and maintain verification infrastructure across RTL, DV, firmware, and system-level flows.
• Monitor and debug daily simulation and emulation regressions; ensure rapid triage.
• Manage release tagging, build readiness, and flow signoff support.
• Collaborate with EDA vendors to improve compile time, run time, and tool performance.
• Maintain Makefiles, build systems, and regression automation.
• Oversee testlists, regression configurations, and execution strategies.
• Coordinate firmware testing and integration with verification environments.
• Manage Git repositories, CI/CD pipelines, and verification automation workflows.
• Work with multi-site teams across India and USA West Coast.

Skills

RTL design

Design Verification

Git

CI/CD

Bash scripting

Python scripting

Tcl scripting

Education

Bachelor's or Master's in EE/CE

Tools

Siemens EDA tools

Job description

We are looking for exceptional talent and leadership to join Fast Growing Startup into Scalable Intelligence, the world's first company developing Agentic Silicon for powering the future of AI.

Founded in 2023, We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and vision.

Design Automation Engineer

At Tsavorite Scalable Intelligence, we are pioneering the semiconductor industry's first Omni Processing Unit (OPU) - a breakthrough composable architecture designed to power the next generation of real-time, multi-modal Agentic AI.

Founded in 2023 by a veteran team from Intel, Nvidia, Qualcomm, and Apple, we are on a mission to eliminate the cost, power, and complexity bottlenecks of legacy GPU systems. Our technology delivers a 10x performance gain at 10% of energy consumption, scaling seamlessly from edge devices to exascale data centers.

Why Engineers Join Us:

• Architectural Innovation: Work on the MultiPlexus fabric, a revolutionary interconnect offering petabyte-scale bandwidth and ultra-low latency.
• Full-Stack Impact: We are building everything from modular chiplets on Samsung's SF4X platform to our Tsavorite AI Orchestration Stack (TAOS), which provides zero-switching-cost compatibility for CUDA-optimized workflows.
• Market Momentum: We emerged from stealth with over $100 million in pre-orders from Global 500 companies and sovereign cloud providers.

Key Links to Include

• Recent News: Tsavorite Emerges with $100M in Orders & 10x Performance (Forbes)

We are looking for a CAD Hardware Engineer with strong RTL Design and Design Verification expertise to own and scale our verification infrastructure across simulation and emulation environments. In this role you'll be building solutions to boost productivity and efficiency of our design and verification teams.

This role is critical to ensuring tool flow stability, performance, and release readiness for large-scale hardware programs. The engineer will work closely with RTL/DV teams and EDA vendors to drive productivity, reliability, and continuous improvement.

You will be involved with building verification infrastructure for a multi-chiplet design that scales beyond just one or two chiplets!

Key Responsibilities

• Own and maintain verification infrastructure across RTL, DV, firmware, and system-level flows
• Monitor and debug daily simulation and emulation regressions, ensuring rapid triage and resolution.
• Manage release tagging, build readiness, and flow signoff support[GW1] [GU2]
• Partner with EDA vendor to improve compile time, run time, and tool performance
• Own and maintain Makefiles, build systems, and regression automation
• Maintain and optimize testlists, regression configurations, and execution strategies
• Maintain firmware testing and integration with verification environments
• Manage Git repositories, CI/CD pipelines, and verification automation workflows
• Work in slurm environment to efficiently use AWS based compute infrastructure.
• Proactively monitor and manage disk usage and storage resources to ensure uninterrupted regressions and work with IT team to ensure proper infrastructure is in place.
• Work with India and USA West Coast based Design and DV teams

Required Qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or related field. 5+ years prior experience and background in VLSI design or DV is required. Strong programming skills in multiple languages (bash, Tcl, Python, Makefile and other scripting languages involved in automation of design/DV flows).
• Good interpersonal skills, quick learner, proactive, innovative, highly motivated, and committed
• Strong experience in RTL design and/or Design Verification
• Hands-on experience with simulation and emulation tool flows
• Solid experience with Git, branching, release management, and CI/CD systems
• Proven ability to manage large-scale regressions and complex verification environments

Preferred Experience

• Direct experience working with Siemens EDA tools
• Familiarity with UVM-based verification methodologies
• Experience supporting firmware bringup in a DV environment