Design Verification Lead

TylSemi, Inc.; Karnataka; Hybrid; INR 4,500,000 - 6,500,000; Full time

Benefits offered by this job

Remote-friendly

Global team

Job summary

TYLsemi, Inc. is seeking a senior verification lead to architect and drive verification for large-scale SoCs targeting AI/HPC. You will build reusable verification platforms and advance portable verification flows to enable scalable, efficient silicon validation.

This role emphasizes leadership in verification architecture, high-performance testbenches, and AI/ML-enabled methodologies, with collaboration across design, architecture, and software teams.

Qualifications

• Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of Design Verification experience with large SoC verification.
• Proven experience defining and deploying verification architectures for complex chips.
• Strong expertise in SystemVerilog and UVM Coverage-driven verification (functional + code coverage).
• Assertion-based verification (SVA).
• Experience with Portable Stimulus (PSS) and cross-level stimulus reuse.
• Experience with industry-standard protocols (PCIe, DDR, Ethernet, CXL, UCIe).
• Deep understanding of SoC architectures in AI, HPC, or Networking domains.
• Experience with multi-IP integration challenges, coherency, high-speed interfaces, and large-scale data movement.
• Strong debugging skills and ability to handle complex system-level issues.

Responsibilities

• Define and drive the overall verification architecture for large-scale SoCs, ensuring scalability from IP → subsystem → full SoC level.
• Architect reusable, modular, and portable verification platforms that can be leveraged across multiple chip programs.
• Establish methodologies for seamless reuse and portability, including Portable Stimulus (PSS)-based verification flows.
• Lead the development of high-performance, coverage-driven testbenches using industry-standard methodologies (e.g., UVM).
• Drive multi-level verification strategies, enabling efficient scaling across Block-level, Multi-block/subsystem level, Full-chip SoC level.
• Define and enforce verification quality metrics, coverage closure strategies, and sign-off criteria.
• Champion a “fail-fast” philosophy to detect issues early and improve overall design quality.
• Drive initiatives toward first-pass silicon success, minimizing escapes and post-silicon debug effort.
• Leverage AI/ML techniques and AI agents to automate testbench generation, improve stimulus generation and coverage closure, and enhance regression efficiency.
• Collaborate with design, architecture, physical design, and software teams to ensure alignment and early issue detection.
• Mentor and guide DV teams on best practices, methodology adoption, and architectural decisions.

Skills

Design Verification

SystemVerilog

UVM

Large SoCs

Automation & AI

Collaboration

Education

Bachelor's or Master's in EE/CE

Tools

Portable Stimulus (PSS)

Job description

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem:how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds thechiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

About TYLsemi, Inc.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem:how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds thechiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

The semiconductor industry is going through its biggest architectural shift in 40 years:

Moore's Law is dead.2nm and beyond delivers marginal performance gains. The future is chiplets, not monolithic dies.Custom silicon is now mainstream.Google, Microsoft, Amazon, Meta, OpenAI — they're all designing their own ASICs. The $50B custom silicon market is growing 30% annually.IO and power are the bottleneck.Solve hard problems and provide something which is a category in itself.Translation:We're entering the market at exactly the moment when every major AI/HPC player needs what we're building, and their alternatives are disappearing.

Culture & Team: How We WorkNo Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

If you have an idea, we test it. If it works, we ship it.No endless meetings, no PowerPoint presentations to convince middle management.Remote-Friendly, Global TeamUS team:Bay Area preferred, but we hire the best people regardless of locationIndia team:Building a world-class design center in Bangalore

Move Fast, Ship Real Products

We're not a research project. We have paying customers, committed capital, and aggressive timelines.

This is a company, not a lifestyle business. We're building to win.

What We Value

• Ownership mindset. You're not here to execute someone else's roadmap.
• Bias for action. We move fast. Analysis paralysis doesn't fly here.
• Deep technical expertise. This is hard engineering. We need people who've shipped real silicon and debugged real hardware.
• Low ego, high standards. We don't care about titles or politics. We care about results.

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

The market is real.

AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.

The team has done this before.

We've built and exited semiconductor companies at scale. This isn't our first rodeo.

The traction is de-risked.

We have LOIs, strategic investors, and a clear path to revenue.

The work is consequential.

You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We would validate design verification lead, high-quality verification strategies for next-generation SoCs targeting AI, HPC, and Networking applications. This role requires deep expertise verifying large and complex SoCs and a passion for building next-gen verification platforms, leveraging automation, portability, and AI-driven methodologies.

What You'll Do

• Define and drive theoverall verification architecturefor large-scale SoCs, ensuring scalability fromIP → subsystem → full SoC level
• Architect and developreusable, modular, and portable verification platformsthat can beleveragedacross multiple chip programs
• Establish methodologies forseamless reuse and portability, includingPortable Stimulus (PSS)-based verification flows
• Lead the development ofhigh-performance, coverage-driven testbenchesusing industry-standard methodologies (e.g., UVM)
• Drivemulti-level verification strategies, enabling efficient scaling across: Block-level, Multi-block/subsystem level, Full-chip SoC level
• Define and enforceverification quality metrics, coverage closure strategies, and sign-off criteria
• Champion a“fail-fast” philosophy to detect issues early and improve overall design quality
• Drive initiatives towardfirst-pass silicon success, minimizing escapes and post-silicon debug effort
• LeverageAI/ML techniques and AI agents to: Automate testbench generation
• Improve stimulus generation and coverage closure
• Enhance regression efficiency and debug productivity
• Enable intelligent verification QA and anomaly detection
• Collaborate closely withdesign, architecture, physical design, and software teams to ensure alignment and early issue detection
• Mentor and guide DV teams onbest practices,methodologyadoption, and architectural decisions

What We’re Looking For

• Bachelor's/Master's degree in Electrical Engineering, Computer Engineering, or related field
• 10+ years of experience inDesign Verification, with significant exposure tolarge SoC verification
• Proven experience in defining and deployingverification architectures for complex chips
• Strongexpertisein: SystemVerilogand UVM Coverage-driven verification (functional + code coverage)
• Assertion-based verification (SVA)
• Hands-on experience withPortable Stimulus (PSS)and cross-level stimulus reuse
• Experience on industry-standard protocols (e.g., PCIe, DDR, Ethernet, CXL, UCIe)
• Deep understanding ofSoC architecturesin AI, HPC, or Networking domains
• Experience withmulti-IP integration challenges, coherency, high-speed interfaces, and large-scale data movement
• Strong debugging skills and ability to handlecomplex system-level issues

Good to Have

• Experience withAI/ML applications in verification workflows
• Exposure toemulation, prototyping, or hybrid verification platforms
• Familiarity withperformance verification and power-aware verification
• Knowledge of industry-standard protocols (e.g., PCIe, DDR, Ethernet, CXL, UCIe)
• Experience buildingverification frameworks reused across multiple tape-outs

Key Attributes

• Strong architectural thinking with asystems-level mindset
• High ownership with aquality-first approach
• Bias towardautomation, reuse, and scalability
• Passion for adoptingcutting-edgetechnologies, especially AI-driven verification
• Ability tooperatein a fast-paced environment with afail-fast, learn-fast attitude
• Excellent collaboration and leadership skills

Success in This Role Looks Like

• High degree ofverification reuse across programs
• Achievement ofcoverage and quality goals within schedule
• Reduction inverification cycle time through automation and AI
• Strongtrack recordoffirst-time silicon success
• Minimal post-silicon escapes and debug cycles