Senior Staff - SOC RTL Design Engineer

TylSemi, Inc.; Karnataka; On-site; INR 2,500,000 - 6,000,000; Full time

Job summary

TYLsemi, Inc. is seeking a highly skilled RTL Designer to develop high-performance, scalable digital designs for next-generation SoCs and chiplets targeting AI, HPC, and Networking applications.

You will own reset sequencing, clocking, power management, and interfaces with firmware collaboration for first-time silicon success. The role requires 12+ years in digital IC design, SystemVerilog expertise, and experience with embedded MCU integration, reset/DFT ownership, and power-aware design.

Qualifications

• 12+ years of digital IC design with at least 5 years owning chip infrastructure — clocking, power management, reset or DFT — at block-lead or subsystem-owner level.
• Experience with embedded microcontroller integration: memory maps, boot ROM, interrupt controllers, and firmware bring-up at hardware level.
• BS/MS in Electrical Engineering, Computer Engineering, or equivalent.

Responsibilities

• Specify and own the reset sequencing architecture.
• Own the secure boot and fuse micro-architecture and design.
• Coordinate with subsystem leads on reference clock distribution and clock-domain crossing at interfaces.
• Collaborate with firmware to define hardware/software interface: interrupt controller, timer, UART/JTAG, and DMA/mailbox channels.
• Own clock-gating implementation strategy and sign-off methodology for dynamic power reduction.
• Define the chip-level power-domain plan and integration of level-shifters and isolation cells.
• Own on-chip power management logic: power-state machine, voltage regulator integration, firmware interface.
• Drive UPF/CPF power intent authoring and sign-off with physical design coordination.
• Own embedded management processor subsystem: processor integration, on-chip SRAM/ROM sizing, boot sequence, OTP interface, firmware environment.
• Define management register map for firmware configuration and telemetry.
• Define on-die temperature sensing integration and thermal throttling hooks.

Skills

RTL Design

digital IC design

clocking

power management

reset/DFT ownership

SystemVerilog

embedded MCU integration

firmware bring-up

clock-domain crossing

secure boot

DFT (design for test)

Education

BS/MS in Electrical Engineering or Computer Engineering

Job description

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds thechiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Why NowThe Market Window

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds thechiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

The Opportunity

The AI infrastructure market is exploding. Every hyperscaler, every cloud provider, every AI company is building custom silicon. But they all face the same problem: how do you connect hundreds of chips, deliver clean power at scale, and move terabits of data without melting the package?

That's what we solve. TYLsemi builds thechiplet infrastructure IP— the IO, power delivery, and interconnect building blocks — that makes AI/HPC systems actually work at scale.

This isn't a nice-to-have. It's the critical path.

Culture & Team: How We Work

No Politics, No Bureaucracy

There are no layers, no approval chains, no corporate theater.

Remote-Friendly, Global Team US team: Bay Area preferred, but we hire the best people regardless of location India team: Building a world-class design center in Bangalore

The Ask

If you're reading this, you're probably comfortable. You have a good job at a stable company with all the benefits.

We're asking you to walk away from that and bet on us.

Here's why you should:

• The market is real. AI infrastructure spending is $200B+ annually and growing 40% YoY. Every hyperscaler needs what we're building.
• The team has done this before. We've built and exited semiconductor companies at scale. This isn't our first rodeo.
• The traction is de-risked. We have LOIs, strategic investors, and a clear path to revenue.
• The work is consequential. You're not optimizing someone's ad click-through rate. You're building the silicon infrastructure that powers AI.

This is the bet. Join us and build something that matters.

Or stay comfortable. No judgment.

But if you're the kind of person who wants to take the shot, we'd love to talk.

READY TO JOIN?

Role Overview

We are looking for a highly skilledRTL Designerto develop high-performance, scalable, and power-efficient digital designs for next-generation SoCs and Chiplets targetingAI, HPC, and Networking applications. This role requires deep expertise in RTL design, micro-architecture, and integration of high-speed interfaces, along with a strong focus onquality, performance, and first-time silicon success.

What You’ll Do

• Specify and own the reset sequencing architecture.
• Own the secure boot and fuse micro architecture and design.
• Coordinate with the subsystem leads on reference clock distribution, clock-domain crossing points at subsystem interfaces.
• Collaborate with the firmware team to define the hardware/software interface: interrupt controller, timer, UART/JTAG debug port, and any DMA or mailbox channels.
• Own the clock-gating implementation strategy: coarse-grain vs. fine-grain gating, ICG cell selection, and sign-off methodology for dynamic power reduction.
• Define the chip-level power-domain plan: which blocks share supplies, where level-shifters and isolation cells are required, and how power states map to the PCIe and UCIe link power management protocols.
• Own the on-chip power management logic: power-state machine, supply sequencing, voltage regulator integration, and the firmware interface for runtime power control.
• Drive power intent (UPF/CPF) authoring and sign-off, coordinating with physical design team on power-domain floorplan, always-on routing, and isolation verification.
• Own the embedded management processor subsystem: processor integration, on-chip SRAM and ROM sizing, boot sequence, fuse and OTP interface, and the firmware execution environment.
• Define the management register map: the address space through which firmware configures operating modes, reads telemetry, controls power states, and manages DFT operations.
• Specify thermal monitoring integration: on-die temperature sensor placement, readout path to the management processor, and thermal throttling hooks.

What We’re Looking For

• 12+ years of digital IC design, with at least 5 years owning chip infrastructure — clocking, power management, reset or DFT — at block-lead or subsystem-owner level.
• Familiarity with embedded microcontroller integration: memory maps, boot ROM, interrupt controllers, and firmware bring-up at the hardware level.
• Experience with reset-domain architecture and reset synchronizer design in multi-power-domain chips.
• Strong SystemVerilog skills for infrastructure RTL: clock-gating cells, power FSMs, scan-enable muxing, and BIST controllers.
• BS/MS in Electrical Engineering, Computer Engineering, or equivalent.

Good to Have

• Background integrating a RISC-V or ARM Cortex-M class processor as a management/configuration engine in a non-CPU chiplet.
• Exposure to hardware security: secure boot, anti-tamper fuse programming, or related infrastructure.