System Architect

Mulya Technologies; Bengaluru; On-site; INR 4,000,000 - 7,000,000; Full time

Job summary

Mulya Technologies is seeking a seasoned Systems Architect to drive end‑to‑end system definition across hardware platforms from edge devices to data center scales. You will orchestrate across Silicon, Packaging, PCB, software, and operations teams to optimize performance, power, and cost.

The role demands 14+ years of experience in hardware architecture, deep PCB and interconnect expertise, and leadership to guide cross‑functional teams toward scalable, producible solutions.

Qualifications

• Experience: 14+ years architecting complex hardware platforms, server builds, or high-speed systems.
• High-Speed PCB & systems: deep expertise in multi-layer board design, SI/PI budgets, and thermal/power integration.
• Interconnect Standards: 112G/224G PAM4 SerDes, PCIe Gen 5/6/7, CXL, Ethernet.
• Racks Form Factors & Cabling: knowledge of OCP, OSFP/QSFP-DD, backplanes, AOC solutions.
• STCO & Problem Solving: silicon–package–PCB co-optimization and cross-domain issue resolution.
• Leadership: strong interpersonal skills to align multi-disciplinary teams.
• Education: Master’s degree in computer engineering, EE, CS, or related domain.

Responsibilities

• Drive architecture from silicon to full datacenter deployments and edge platforms, balancing performance, power, thermal, and total cost of ownership.
• Lead STCO across Silicon, Packaging, PCB, Software, and Operations to optimize interfaces and power delivery.
• Define high-speed channel envelopes for scale-up/scale-out solutions with 112G-224G SerDes and PDN considerations.
• Specify mechanical/thermal architectures for edge environments and rack-scale platforms with cooling solutions.
• Collaborate with customers and partners to align roadmaps and drive configurations to production.
• Mentor teams and oversee lifecycle from concept to volume production.

Skills

System architecture

Cross-domain design

High-speed PCB

SerDes standards

Leadership

Education

Master's degree in computer/electrical engineering or CS

Job description

nWe are looking for exceptional talent and leadership to join Fast Growing Startup into Scalable Intelligence, the world’s first company developing Agentic Silicon for powering the future of AI.Founded in 2023, We have deep customer engagements across America, Europe, and Asia, and demonstrated functional prototypes to prove our concept and visi

o
.Key Link

• s to IncludeOfficial Website: tsavoritesi.comLinkedIn Page
• e | LinkedInRecent News
• : Tsavorite Emerges with $100M in Orders & 10x Performance(Forbe

In
We are seeking a Systems Architect to drive end-to-end system definition and architecture across the full hardware spectrum—from compact Edge & Physical AI devices to high-density, multi-megawatt OCP datacenter rac

ks.In this role, you will lead System-Technology Co-Optimization (STCO) from the chip out to the datacenter, collaborating with Silicon, Advanced Packaging, Board Design, SI/PI, and Thermal/Mechanical teams. Responsible for the Optimized product solution based on the power, performance and cost of different configurations. Collaborate with key customers and system partners on the product solutio

ns.Key Responsibilit

• iesEnd-to-End System Definition: Drive architecture from the silicon chip out to full datacenter deployments and edge platforms, balancing performance, power, thermals, and total cost of ownership (TC
• O).STCO & Cross-Domain Co-Design: Partner across Silicon, Advanced Packaging (substrates, 2.5D/3D, BGA ball maps), PCB Design, Software, and Operations to optimize interfaces, escape routing, power delivery, and system bring-
• up.Board, SI/PI & Power Architecture: Architect full-path channel envelopes for Scale-up and Scale-out solutions with data rates enveloping 112G-224G Serdes. Define high-speed multi-layer PCB solution, loss/crosstalk budgets, and Power Delivery Networks (PDN)—from edge DC inputs to 48V/54V OCP busbars and 1000A+ transient VR
• Ms.Thermals & Physical Form Factors: Specify mechanical and thermal architectures across edge environments and OCP rack-scale platforms (air cooling, cold plates, and direct-to-chip liquid cooling/CDU
• s).Scale-Up & Scale-Out Interconnects: Define architectures for front-panel interfaces (OSFP, QSFP-DD), high-speed backplane connectors, AECs, and AOCs/optical transceive
• rs.Ecosystem & Lifecycle Leadership: Collaborate with key customers, ODMs, and component suppliers to align technology roadmaps and take systems from concept through volume producti

on.Qualifications & Ski

llsRequired Qualificati

• onsExperience: 14+ years architecting complex hardware platforms, server builds, or high-speed syste
• ms.High-Speed PCB & Systems: Deep expertise in high-speed, multi-layer product board design, SI/PI channel budgeting, and server-level mechanical, power, and thermal integrati
• on.Interconnect Standards: 112G/224G PAM4 SerDes, PCIe Gen 5/6/7 (128 Gbps/lane), CXL, and Ethernet standa
• rdsForm Factors & Cabling: Working knowledge of OCP standards (ORv3, busbars, OAM/UBB), OSFP/QSFP-DD, backplanes, AEC, and AOC solutio
• ns.STCO & Problem Solving: Demonstrated success with Silicon–Package–PCB co-optimization and hands-on resolution of complex hardware/software issu
• es.Leadership: Strong interpersonal skills to align multi-disciplinary teams with a proactive, learning-oriented minds
• et.Education: Master’s degree in computer engineering, Electrical Engineering, Computer Science, or related domai