Senior Circuit Silicon Correlation DFT Engineer

NVIDIA AI; Bengaluru; On-site; INR 4,200,000 - 6,400,000; Full time

Job summary

NVIDIA is seeking a senior VLSI/DFT engineer in Bengaluru to drive design-for-test methodologies for deep submicron processor projects. You will develop ATPG patterns, verify RTL and gate-level designs, diagnose root causes of failures, and advance RAM testing techniques across multiple RAM types and processes.

Required are 8+ years in Electrical/Electronics, strong DFT knowledge including scan, BIST, fault models, and experience with Tessent pattern generation and VLSI simulators.

Qualifications

• BSEE required or MS preferred in Electrical/Electronics with 8+ years experience
• Strong knowledge of Design-for-test (DFT) and logic design
• Solid understanding of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation
• Experience bringing up RTL/gate level simulation and debugging testcases
• RAM functionality/architecture basics helpful
• Experience with VLSI simulation tools like VCS
• Experience with pattern generation using Tessent
• Proficiency in scripting languages (Python, Perl, Tcl, Make)
• Prior STA experience and basic circuit concepts
• Post-Silicon data gathering experience is a plus

Responsibilities

• Participate in ground breaking Processor design and debug in deep submicron technologies
• Work in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models
• Responsible for generating ATPG patterns for Silicon speed path debug
• RTL and gate level verification for ATPG, non-ATPG patterns
• Correlating diagnosis result to map to real design failures and root cause to learnings for pre-silicon design sign off
• RAM correlation by studying RAM circuit failure mechanisms and understanding their limits on silicon
• Bring in more circuit understanding into the RAM testing methods across RAM types, chips and processes
• Develop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and around RAM

Skills

Scripting languages (Python Perl Tcl(M

Education

BSEE / MS in Electrical or Electronics Engineering

Tools

VCS (VLSI simulator)

Tessent pattern generation

Job description

Job Requisition ID

JR2012806

Job Category

Engineering

Time Type

Full time

NVIDIA has continuously reinvented itself over two decades. Our invention of the GPU in 1999 sparked the growth of the PC gaming market, redefined modern computer graphics, and revolutionized parallel computing. NVIDIA is a “learning machine” that constantly evolves by adapting to new opportunities that are hard to solve, that only we can tackle, and that matter to the world. This is our life’s work , to amplify human imagination and intelligence. Make the choice to join us today.

What Will You Be Doing

• Participate in ground breaking Processor design and debug in deep submicron technologies.
• Work in a multi functional team passionate about Silicon characterization and correlation to pre-Silicon Performance and Power models.
• Responsible for generating ATPG patterns for Silicon speed path debug.
• RTL and gate level verification for ATPG, non-ATPG patterns.
• Correlating diagnosis result to map to real design failures. Root cause the same feed learnings to pre-silicon design sign off parameters.
• RAM correlation by studying RAM circuit failure mechanisms and understanding their limits on silicon
• Bring in more circuit understanding into the RAM testing methods across RAM types, chips and processes and improve correlation in the long run
• Develop new methodologies using DFT infrastructure to analyze components of mis-correlation in logic and in/around RAM.

What We Need To See

• BSEE required/MS preferred in Electrical or Electronics Engineering with 8+ years experience; Prior leadership experience a certain plus.
• Good understanding of Design-for-test(DFT) and logic design is required.
• Must possess a solid understanding of DFT including scan, BIST, on-chip scan compression, fault models, ATPG, and fault simulation.
• Must have some experience in bringing up RTL/gate level simulation, writing testcase and debugging it.
• Basics of circuits and RAM functionality/architecture will be helpful.
• Experience in VLSI simulation tools like VCS etc
• Experience with pattern generation using tools such as tessent.
• Proficiency in scripting language, such as, Python, Perl, Tcl, Make and automation methods/algorithms would be good.
• Prior experience in STA and basic understanding of circuit concepts will help in the role.
• Post-Silicon data gathering experience is a plus.

NVIDIA is widely considered to be one of the technology world’s most desirable employers. We have some of the most forward-thinking and talented people in the world working for us. If you're creative, autonomous and love a challenge, we want to hear from you.