Senior Analog Layout Engineer

Cyient Limited; Telangana; On-site; INR 2,400,000 - 4,200,000; Full time

Job summary

Cyient Limited is seeking a Senior Analog Layout Engineer with experience in FinFET technology nodes (7nm and below) and high-speed analog/mixed-signal layout design. You will translate schematics into high-quality physical layouts, ensuring compliance with foundry rules and performance requirements.

You will work closely with circuit designers and verification teams to develop robust layouts for high-speed IPs, ensuring successful DRC/LVS closure and efficient post-layout verification.

Qualifications

• Translate schematics into physical layouts adhering to foundry design rules.

Responsibilities

• Translate schematics into physical layouts meeting foundry rules.
• Collaborate with circuit designers and verification teams for post-layout verification and robust IP layouts.

Skills

Analog Layout

FinFET

DRC/LVS

High-speed design

Job description

We are seeking a highly skilled Senior Analog Layout Engineer with strong experience in advanced FinFET technology nodes (7nm and below) and high-speed analog/mixed-signal layout design. The ideal candidate will be responsible for translating schematics into high-quality physical layouts while ensuring compliance with foundry design rules, performance requirements, and project specifications.

The engineer will work closely with circuit designers and verification teams to develop robust layouts for high-speed analog and mixed-signal IPs, ensuring successful DRC/LVS closure and post-layout verification.