Senior Analog Layout Engineer

KriSemi Design Technologies; Bengaluru; On-site; INR 1,200,000 - 1,800,000; Full time

Job summary

KriSemi Design Technologies in Bengaluru is seeking an Analog Layout Engineer to drive custom block layouts for advanced technology nodes, including PLLs, Bandgap and ADC/DAC. You will deliver layouts with high accuracy using industry-standard CAD tools and ensure reliability of electrical parameters.

Your responsibilities include chip-level integration, physical verification, and electrical closure across digital, analog and mixed-signal blocks, with familiarity on 3nm/2nm processes.

Qualifications

• Expertise in custom block layout for analog IPs (PLL/Bandgap/ADC/DAC).
• Strong proficiency with CAD tools used for layout and verification.
• Sound understanding of layout electrical parameters and closure.
• Experience across digital, analog and mixed-signal layouts.
• Familiarity with reliability concepts for layout.

Responsibilities

• Execute full custom layouts in cutting-edge technology nodes.
• Handle sub cells/leaf cells to build IP/macro using CAD tools.
• Chip-level integration, physical verification, and electrical closure.
• Gain exposure to other fields of custom layout.
• Work with 3nm/2nm processes and ensure NDA commitments.

Skills

Layout design

CAD tools

Analog layout

Mixed-signal layout

Electrical parameter knowledge

Tools

Virtuoso

Calibre

DRC

LVS

Job description

Key Responsibilities/Preferred Experience:

The role involves execution in the field of full custom layouts in cutting edge technology nodes. It will require a good layout electrical parameter knowledge along with quick learning capabilities.

Candidate should be able to handle sub cells/leaf cells that are needed to build IP/macro using CAD tools

Chip level integration, physical verification and electricals’ closure

Candidate will be exposed/experienced to various other fields of custom layout

Custom layout expertise in lower technology

Digital, Analog and mixed signal layout.

Good understanding of reliability concepts

Good understating of layout electrical parameters and closure

This is for Analog Layout Engineers having exp in custom block layout like PLL, Bandgap, ADC, DAC etc. and Virtuoso, Calibre, DRC, LVS

Requires TSMC 3nm and 2nm 3-way NDA in place