RTL DESIGN ENGINEER

Azista Space; Bengaluru; On-site; INR 1,800,000 - 3,200,000; Full time

Job summary

Azista Space seeks an experienced RTL Design Engineer to own the full digital logic lifecycle for flight-critical satellite subsystems. You will architect, implement, and validate high-speed hardware modules designed to withstand orbital radiation and thermal stress.

In this role, you will drive synthesis, timing closure, and CDC verification across FPGAs, with heavy focus on Verilog/SystemVerilog/VHDL, SpaceWire, PCIe, and AXI4 interfaces.

Qualifications

• B.E./B.Tech or M.E./M.Tech in ECE, VLSI, Microelectronics, Embedded Systems, or equivalent.
• 3 to 8+ years of RTL design, timing closure, and FPGA implementation.
• Expert-level mastery of Verilog, SystemVerilog, or VHDL paired with deep experience in Xilinx Vivado, STA debugging, and SDC/XDC constraint development.
• Proven track record implementing AXI4, PCIe, Ethernet, SPI, I2C, UART, or DDR memory controllers.
• Hands-on hardware bring-up, bench testing, and troubleshooting via logic analyzers.

Responsibilities

• RTL Architecture & Logic Design: Architect, code, and sanitize designs in Verilog, SystemVerilog, or VHDL ensuring latch‑free, lint‑clean delivery.
• Space Radiation Hardening: Apply radiation mitigation techniques in RTL, including TMR, EDAC/ECC scrubbing, SEU/SEFI-tolerant encoding.
• Synthesis & Timing Closure: Drive implementation in Vivado, Quartus, or Libero; write/debug SDC/XDC constraints and resolve setup/hold issues.
• High‑Speed Protocol Integration: Integrate AXI4, PCIe, DDR3/4, SpaceWire, SpaceFibre, CAN, SPI/I2C/UART.
• CDC Sign‑Off & Verification: Enforce CDC discipline using Questa CDC or SpyGlass; create self‑checking testbenches and gate‑level sims.
• Board Bring‑Up & Lab Validation: Partner with hardware teams during bench testing using logic analyzers and oscilloscopes.

Skills

RTL Design

Verilog

SystemVerilog

VHDL

Synthesis

Timing Closure

Space Radiation Hardening

AXI4

PCIe

Ethernet

SPI

I2C

UART

SpaceWire

SpaceFibre

CAN

Education

B.E./B.Tech or M.E./M.Tech in ECE

Tools

Vivado

Quartus

Libero

Questa CDC

SpyGlass

Job description

Join a team that is redefining the accessibility of space. Azista space is a transformative force in the global aerospace sector, uniquely positioned at the intersection of indigenous innovation and industrial scalability. Operating India’s first private-sector satellite mass-production facility in Ahmedabad, we have bridged the gap between complex engineering and high-volume manufacturing.

As a vertically integrated leader, we provide end-to-end solutions from the precision design of satellite buses and advanced payloads to mission management and communication systems. We don’t just build hardware, we are democratizing the final frontier by providing global clientele with the cost-effective, high-performance technology needed to power the next generation of orbital missions. At Azista, you won't just be starting a job, you’ll be fuelling the future of space exploration.

JOB SUMMARY:

Azista Space is a transformative force in the global aerospace sector, uniquely positioned at the intersection of indigenous innovation and industrial scalability. Operating India’s first private-sector satellite mass-production facility, we provide complete, end-to-end space solutions—from precision design of satellite buses and advanced payloads to mission management and high-throughput communication systems.

As a RTL Design Engineer , you will own the full digital logic lifecycle for flight‑critical satellite subsystems. You will architect, implement, and validate high‑speed, fault‑tolerant hardware modules engineered to execute flawlessly under extreme orbital radiation and thermal stress.

In this role, your technical impact will directly drive functional closure on space‑grade FPGAs, zero‑defect hardware bring‑up, precise static timing closure (STA), and successful execution across major spaceflight design reviews (PDR/CDR).

KEY RESPONSIBILITIES:

• RTL Architecture & Logic Design: Architect, code, and sanitize complex synthesizable designs (FSMs, FIFOs, pipelines, ALUs, arbiters) in Verilog, SystemVerilog, or VHDL ensuring latch‑free, lint‑clean delivery.
• Space Radiation Hardening: Implement robust radiation mitigation techniques in RTL, including Triple Modular Redundancy (TMR), EDAC/ECC memory scrubbing, SEU/SEFI‑tolerant safe‑state FSM encoding, and graded reset hierarchies.
• Synthesis & Timing Closure: Drive target implementation in Xilinx Vivado, Intel Quartus, or Microchip Libero; independently write/debug SDC/XDC constraints and resolve complex setup/hold violations to achieve STA sign‑off.
• High‑Speed Protocol Integration: Integrate and validate high‑speed bus fabrics and communication interfaces including AXI4, PCIe, DDR3/4, SpaceWire, SpaceFibre, CAN, and standard low‑speed buses (SPI, I2C, UART, MIL‑STD‑1553).
• CDC Sign‑Off & Verification: Enforce rigorous Clock Domain Crossing (CDC) discipline using Questa CDC or Synopsys SpyGlass CDC; create self‑checking testbenches and execute gate‑level simulations with SDF back‑annotation.
• Board Bring‑up & Lab Validation: Partner with hardware teams during bench testing and silicon bring‑up, utilizing logic analyzers and high‑speed oscilloscopes for physical hardware debugging.

WHAT WE’RE LOOKING FOR?

• Education: B.E./B.Tech or M.E./M.Tech in ECE, VLSI, Microelectronics, Embedded Systems, or equivalent.
• Experience: 3 to 8+ years of hands‑on experience in RTL design, timing closure, and FPGA implementation.
• HDL & Tool Mastery: Expert‑level mastery of Verilog, SystemVerilog, or VHDL paired with deep experience in Xilinx Vivado, STA debugging, and SDC/XDC constraint development.
• Protocol & Interface Proficiency: Proven track record implementing AXI4, PCIe, Ethernet, SPI, I2C, UART, or DDR memory controllers.
• Lab Debugging: Demonstrated experience with hands‑on hardware bring‑up, bench testing, and troubleshooting via logic analyzers.

NICE-TO-HAVE SKILLS

• Direct domain background in Spacecraft Avionics, Satellite Communications, Defense Electronics, or Aerospace systems.
• Direct hands‑on experience with rad‑tolerant target devices (e.g., Microchip RTG4 / RT PolarFire, AMD‑Xilinx XQR Kintex/Virtex UltraScale+).
• Testbench and workflow automation using Python, Tcl, or MATLAB scripting.

WHY JOIN US?

• Pioneer Commercial Spaceflight: Work at the forefront of private satellite mass production and see your RTL designs actively deployed into orbit.
• Full‑Lifecycle Engineering: Experience true end‑to‑end ownership—watch your source code transition directly onto physical silicon, flight PCBs, and orbiting spacecraft.
• High‑Impact Innovation Culture: Collaborate in an agile, fast‑paced environment engineered specifically for hardware innovators with minimal administrative overhead.
• Competitive Growth & Scale: Benefit from competitive compensation packages, continuous technical leadership opportunities, and clear career progression in a rapidly scaling aerospace leader.