Lead-FPGA/RTL Design

Digantara; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Benefits offered by this job

Competitive incentives

Startup-style culture

Job summary

Digantara seeks a hands-on Lead-FPGA/RTL Design engineer to develop reliable RTL modules for satellite payloads with image acquisition and edge processing capability, enabling Space Situational Awareness. You will mentor a team of RTL design engineers to deliver robust designs.

Ideal candidate has extensive end-to-end FPGA experience, leads a design team, and collaborates with satellite electrical and embedded hardware teams to meet stringent space-grade requirements. Hebbal, Bengaluru location.

Qualifications

• B.E./B.Tech in Electronics Engineering or M.Tech/M.E or PhD in Microelectronics/VLSI/Embedded systems.
• 8+ years in design to hardware life cycle of high-speed FPGA based digital systems with team leadership.
• Strong proficiency in VHDL/Verilog and FPGA flow using Vivado/Libero; scripting TCL/Python/Shell.
• Deep understanding of FPGA architecture for reusable RTL implementations.
• Experience with high-speed memory interfaces (DDR3/4/5) and LVDS and protocols like Camera link, Ethernet, SpaceWire.
• Experience with FPGA/SoC development kits and lab test equipment.

Responsibilities

• Develop the FPGA design architecture for Payload electronics to enable on-board image capture and processing.
• Lead a team of FPGA design engineers through micro-architecture, RTL design, verification and validation.
• Mentor engineers to write concise, resource-efficient RTL code for satellite payloads.
• Review RTL code, verification, validation, and board-level test results across the lifecycle.
• Plan and execute tests on evaluation boards/prototype hardware to validate RTL designs.
• Contribute to evolving best coding practices in verification and validation methods.

Skills

RTL design leadership

VHDL/Verilog

FPGA design

High-speed digital systems

DDR memory interfaces

Lab testing and equipment

TCL/Python/Shell scripting

Education

B.E./B.Tech in Electronics Engineering or M.Tech/M.E or PhD in Microelectronics/VLSI/Embedded systems

Tools

Vivado

Libero EDA

Job description

Digantara is a leading Space Surveillance and Intelligence company focused on ensuring orbital safety and sustainability. With expertise in space-based detection, tracking, identification, and monitoring, Digantara provides comprehensive domain awareness across regimes, allowing end users to have actionable intelligence on a single platform. At the core of its infrastructure lies a sophisticated integration of hardware and software capabilities aligned with the key principles of situational awareness: perception (data collection), comprehension (data processing), and prediction (analytics). This holistic approach empowers Digantara to monitor all Resident Space Objects (RSOs) in orbit, fostering comprehensive domain awareness.

Digantara is looking for a passionate Lead-FPGA/RTL Design engineer to develop reliable, robust and reusable RTL modules for satellite payload, which is capable of image acquisition and edge processing, aimed at Space Situational Awareness (SSA). The Lead engineer will be responsible for mentoring a team of RTL design engineers.

Why Us

• Competitive incentives, galvanizing workspace, blazing team, frequent outings—pretty much everything you have heard about a startup + you get to work on space technology.
• Hustle in a well-funded startup allowing you to take charge of your responsibilities and create your moonshot.

Ideal Candidate

A Hands-on technical leader with proven expertise in end-to-end design and development of FPGA based high-speed digital systems for Satellite Payload/Bus electronics/Ground-based imaging systems.

Responsibilities

Actively collaborate with satellite electrical systems and embedded hardware engineers to carry out trade-off studies and derive the FPGA functional requirements.

• Develop the FPGA Design architecture of the Payload electronics to accomplish on-board image capture and processing.
• Lead a team of FPGA Design engineers to develop micro-architecture, RTL design, verification and validation plans.
• Mentor the design engineers to develop concise, resource efficient RTL code for satellite payloads.
• Review the RTL code, verification and validation, board level test results throughout the development lifecycle.
• Plan and execute the tests on the evaluation boards/prototype hardware to validate the RTL design.
• Contribute to evolve the best coding practices, verification and validation methods.

Required Qualifications

• B.Tech/B.E in Electronics Engineering or M.Tech/M.E or PhD degree in Microelectronics/VLSI/Embedded systems/Electronics systems.
• 8+ years of demonstrated experience in design to hardware implementation life cycle of high-speed FPGA based digital systems, with experience of leading a design team.
• Strong proficiency in VHDL/Verilog with expertise in FPGA design flow using Vivado/Libero EDA tools and familiarity with scripting (TCL/Python/Shell).
• Deep understanding of FPGA architecture and techniques for reliable, resource optimal, reusable RTL implementation.
• Expertise in troubleshooting RTL observations during hardware development lifecycle.
• Proven expertise in handling High-speed memory interfaces (DDR 3/4/5), High-speed I/O interfaces (LVDS) and protocols such as Camera link, Ethernet, SpaceWire.
• Proficiency in working with FPGA/SoC development kits and electronic test equipment at Lab.

Preferred Skills

• Knowledge of algorithm implementation in MATLAB/Python.
• Familiarity with digital image processing techniques.
• Understanding the satellite payload development lifecycle is a significant plus.
• Familiarity with the standards for satellite hardware development is an advantage.
• Knowledge of the latest advancements in FPGA/SoC-based satellite payload electronics development.

General Requirements

• Ability to work in a mission-focused, operational environment.
• Ability to think critically and make independent decisions.
• Interpersonal skills to enable working in a diverse and dynamic team.
• Maintain a regular and predictable work schedule.
• Writing and delivering technical documents and briefings.
• Verbal and written communication skills, as well as organisational skills.
• Travel occasionally as necessary.

Job Location: Hebbal, Bengaluru.