ROCKET LOT ALPHA - Principal Engineer Digital Design

Infineon Technologies AG; Bengaluru; On-site; INR 3,500,000 - 5,500,000; Full time

Job summary

Infineon Technologies AG in Bengaluru seeks an experienced Multi Phase Controller IP Lead responsible for end-to-end control- and filter-centric digital IP development. You will align System modelling, Analog, RTL, DV, and DMS/AMS teams to meet functional, performance, latency, and integration goals.

You will drive architecture closure, verify fixed-point implementations, and manage RTL data paths, interfaces, and verification strategies while coordinating with cross-functional teams.

Qualifications

• Bachelor’s or Master’s degree in Electrical Engineering.
• Strong experience leading digital or mixed-signal-adjacent IP development.
• Strong understanding of control loops, DSP/filter implementations, or fixed-point digital signal processing.

Responsibilities

• Own end-to-end IP definition from requirements through architecture, implementation, verification, and handoff.
• Translate system and product requirements into a clear IP micro-architecture and execution plan.
• Drive closure on algorithm intent, control behavior, filter architecture, latency budgets, and implementation trade-offs.
• Review and converge control/filter algorithm definition, sampling intent, and expected behavior with signal-processing architects.
• Drive fixed-point architecture decisions including numeric precision, dynamic range, saturation, rounding, scaling, and pipeline placement.
• Oversee RTL architecture for filter data path, coefficient programming, update paths, loop delays, state machines, and control logic.
• Own top-level design decisions affecting timing, CDC, reset strategy, area, power, and implementation robustness.
• Guide register architecture, status/control visibility, firmware programmability, and system integration behavior.
• Drive architecture and RTL for AHB/PM Bus/AVS or other system-facing interfaces, including arbitration and error handling.
• Define verification goals and signoff expectations jointly with DV and AMS verification leads.
• Ensure availability of golden models, bit-true checking strategy, coverage goals, and end-to-end latency checks.
• Drive closure on corner cases including overflow, convergence, saturation recovery, limit cycles, reset behavior, and protocol exceptions.
• Ensure analog assumptions, abstraction boundaries, and mixed-signal interaction points are verified appropriately.
• Review and close functional gaps across RTL, DV, DMS/AMS, and system validation.
• Break down execution into work packages, milestones, dependencies, and risk mitigation plans.

Skills

IP leadership

DSP/Fixed-point

Control loops

RTL knowledge

Education

Bachelor’s or Master’s degree in Electrical Engineering

Tools

RTL design

Job description

The Multi Phase controller IP Lead is responsible for end-to-end definition, execution, and delivery of a control- and filter-centric signal processing digital IP that interfaces with high complexity AFEs. This role drives architecture closure across algorithm intent, fixed-point implementation, RTL micro-architecture, register/bus interfaces, verification strategy, and implementation readiness. The IP Lead aligns System modelling, Analog, RTL, DV, and DMS/AMS teams to ensure the IP meets functional, performance, latency, quality, and integration goals.

Your Role

Key responsibilities in your new role

Technical Ownership

• Own end-to-end IP definition from requirements through architecture, implementation, verification, and handoff.
• Translate system and product requirements into a clear IP micro-architecture and execution plan.
• Drive closure on algorithm intent, control behavior, filter architecture, latency budgets, and implementation trade-offs.
• Review and converge control/filter algorithm definition, sampling intent, and expected behavior with signal-processing architects.
• Drive fixed-point architecture decisions including numeric precision, dynamic range, saturation, rounding, scaling, and pipeline placement.
• Oversee RTL architecture for filter data path, coefficient programming, update paths, loop delays, state machines, and control logic.
• Own top-level design decisions affecting timing, CDC, reset strategy, area, power, and implementation robustness.
• Guide register architecture, status/control visibility, firmware programmability, and system integration behavior.
• Drive architecture and RTL for AHB/PM Bus/AVS or other system-facing interfaces, including arbitration and error handling.
• Define verification goals and signoff expectations jointly with DV and AMS verification leads.
• Ensure availability of golden models, bit-true checking strategy, coverage goals, and end-to-end latency checks.
• Drive closure on corner cases including overflow, convergence, saturation recovery, limit cycles, reset behavior, and protocol exceptions.
• Ensure analog assumptions, abstraction boundaries, and mixed-signal interaction points are verified appropriately.
• Review and close functional gaps across RTL, DV, DMS/AMS, and system validation.
• Break down execution into work packages, milestones, dependencies, and risk mitigation plans.

Your Profile

Qualifications and skills to help you succeed

• Bachelor’s or Master’s degree in Electrical Engineering,
• Strong experience leading digital or mixed-signal-adjacent IP development.
• Strong understanding of control loops, DSP/filter implementations, or fixed-point digital signal processing.

Contact: [e-mail]

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