Product Engineer - Physical Design

Siemens EDA (Siemens Digital Industries Software); Bengaluru; On-site; INR 900,000 - 1,300,000; Full time

Job summary

Siemens EDA (Siemens Digital Industries Software) in Bengaluru seeks an experienced Physical Design Engineer to develop and optimize placement, CTS, and routing flows for 7nm/5nm design nodes, while mentoring juniors and leading technical projects. You will provide expert problem resolution and customer training on Aprisa tools to ensure successful deployment.

You will tackle timing, power, and area trade-offs, collaborate with customers on architectural direction, and push for innovative

Qualifications

• Proven experience in physical design with mainstream place and route tools (minimum 2 tape-out projects).
• Hands-on expertise in placement, CTS, routing, and timing closure of complex blocks and full-chip designs.
• Strong understanding of timing, power, and area trade-offs with ability to optimize quality of results.
• Excellent verbal and written communication skills with strong presentation abilities.
• Problem-solving and debugging expertise in complex design scenarios.
• Bachelor's degree in Electronics and Communication, Electrical, or Telecom Engineering.

Responsibilities

• Design, develop, modify, and implement software programming for products with focus on surpassing customer expectations
• Develop flow and methodology for placement, clock tree synthesis (CTS), and routing on advanced process nodes (7nm and 5nm)
• Solve critical design challenges for customers to achieve desired performance, area, and power targets
• Provide technical leadership and mentorship to junior engineers and guide teams on complex projects
• Deliver training and technical support to customers using Aprisa tools, ensuring successful tool adoption and deployment
• Collaborate with customers on future upgrades and product enhancements, influencing technical direction for product areas
• Promote innovation by introducing new technologies and methodologies into physical design workflows

Skills

Physical design

Placement/CTS/Routing

Timing closure

Communication

Problem solving

Mentoring

Education

Bachelor's degree in Electronics and Communication, Electrical, or Telecom Engineering

Master's degree in VLSI or Microelectronics (preferred)

Tools

Synopsys ICC2

Cadence Innovus

Aprisa

Job description

Position Overview

We are passionate about innovations that mean real progress, and we are curious about technologies that still need to be developed. In this role, you'll work on cutting‑edge 7nm and 5nm designs with various customers, developing flow and methodology for placement, CTS, and routing using Aprisa place and route tools. You'll provide expert problem resolution and technical leadership, helping customers achieve desired performance, area, and power targets while delivering training and technical support. This is an opportunity to influence technical direction, mentor junior engineers, and drive innovation in physical design methodologies.

Key Responsibilities

• Design, develop, modify, and implement software programming for products with focus on surpassing customer expectations
• Develop flow and methodology for placement, clock tree synthesis (CTS), and routing on advanced process nodes (7nm and 5nm)
• Solve critical design challenges for customers to achieve desired performance, area, and power targets
• Provide technical leadership and mentorship to junior engineers and guide teams on complex projects
• Deliver training and technical support to customers using Aprisa tools, ensuring successful tool adoption and deployment
• Collaborate with customers on future upgrades and product enhancements, influencing technical direction for product areas
• Promote innovation by introducing new technologies and methodologies into physical design workflows

Qualifications

Required:

• Proven experience in physical design with mainstream place and route tools (minimum 2 tape-out projects)
• Hands‑on expertise in placement, CTS, routing, and timing closure of complex blocks and full‑chip designs
• Strong understanding of timing, power, and area trade‑offs with ability to optimize quality of results
• Excellent verbal and written communication skills with strong presentation abilities
• Problem‑solving and debugging expertise in complex design scenarios
• Bachelor's degree in Electronics and Communication, Electrical, or Telecom Engineering

Preferred:

• Hands‑on experience with commercial place and route tools such as Synopsys ICC2, Cadence Innovus, or Aprisa
• Experience delivering designs with multiple voltage islands and top‑level floor planning
• Master's degree in VLSI or Microelectronics
• Ability to pick up new flows and learn on the job while driving quality improvements