Pro FPGA Design Engineer

Happiest Minds Technologies; Bengaluru; On-site; INR 1,500,000 - 2,500,000; Full time

Job summary

A leading technology firm in Bengaluru is seeking a skilled ProFPGA Design Engineer with 4 to 12 years of experience. You will develop and implement high-performance FPGA designs and perform Static Timing Analysis (STA). The ideal candidate has expertise in ASIC prototyping, RTL design using Verilog/SystemVerilog, and familiarity with UVM-based verification environments. Join a dynamic team and contribute to cutting-edge projects in FPGA development.

Qualifications

• 4 to 12 years of experience in FPGA development and ASIC prototyping.
• Strong understanding of RTL design using Verilog/SystemVerilog.
• Experience with timing closure techniques and UVM-based verification.

Responsibilities

• Develop and implement FPGA-based designs, including coding and synthesis.
• Perform Static Timing Analysis (STA) and drive timing closure.
• Bring up and verify ported RTL in an existing UVM-based verification environment.

Skills

FPGA design

ASIC prototyping

Static Timing Analysis (STA)

Verilog/SystemVerilog

UVM-based verification

Board bring-up

Baremetal driver development

Job description

We are looking for a skilled ProFPGA Design Engineer with 4 to 12 years of experience in FPGA development, ASIC prototyping, and validation. You will be working on high-performance designs, contributing across the full development lifecycle—from RTL porting to board bring-up and verification.

• Develop and implement FPGA-based designs, including coding and synthesis
• Perform Static Timing Analysis (STA) and drive timing closure
• Port ASIC RTL to FPGA platforms efficiently
• Define and execute partitioning strategies for large designs
• Bring up and verify ported RTL in an existing UVM-based verification environment
• Perform board bring-up and debugging
• Develop and enable baremetal drivers for ASIC RTL on FPGA platforms
• 4–12 years of hands-on experience in FPGA design and development
• Strong understanding of RTL design (Verilog/SystemVerilog)
• Experience with STA and timing closure techniques
• Proven expertise in ASIC prototyping and FPGA-based validation
• Familiarity with UVM-based verification environments
• Experience with board bring-up and low-level debugging
• Knowledge of baremetal driver development is a strong plus